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61.发明授权公开(公告)号：US06725340B1
公开(公告)日：2004-04-20
申请号：US09588509
申请日：2000-06-06
IPC分类号： G06F9312
CPC分类号： G06F9/30087 , G06F9/3834 , G06F9/3838 , G06F9/3842 , G06F9/3859
摘要： Disclosed is a processor that reduces barrier operations during instruction processing. An instruction sequence includes a first barrier instruction and a second barrier instruction with a store instruction in between the first and second barrier instructions. A store request associated with the store instruction is issued prior to a barrier operation associated with the first barrier instruction. A determination is made of when the store request completes before the first barrier instruction has issued. In response, only a single barrier operation is issued for both the first and second barrier instructions. The single barrier operation is issued after the store request has been issued and at the time the second barrier operation is scheduled to be issued.
摘要翻译： 公开了一种在指令处理期间减少屏障操作的处理器。 指令序列包括在第一和第二屏障指令之间具有存储指令的第一屏障指令和第二屏障指令。 在与第一屏障指令相关联的屏障操作之前发出与存储指令相关联的存储请求。 确定存储请求何时在第一个屏障指令发出之前完成。 作为响应，仅为第一和第二屏障指令发出单个屏障操作。 单个屏障操作在存储请求已经被发出之后并且在第二屏障操作被安排发布的时候发出。
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62.发明授权Dynamic hardware and software performance optimizations for super-coherent SMP systems 失效超连贯SMP系统的动态硬件和软件性能优化公开(公告)号：US06704844B2
公开(公告)日：2004-03-09
申请号：US09978361
申请日：2001-10-16
IPC分类号： G06F1210
CPC分类号： G06F12/0831
摘要： A method for increasing performance optimization in a multiprocessor data processing system. A number of predetermined thresholds are provided within a system controller logic and utilized to trigger specific bandwidth utilization responses. Both an address bus and data bus bandwidth utilization are monitored. Responsive to a fall of a percentage of data bus bandwidth utilization below a first predetermined threshold value, the system controller provides a particular response to a request for a cache line at a snooping processor having the cache line, where the response indicates to a requesting processor that the cache line will be provided. Conversely, if the percentage of data bus bandwidth utilization rises above a second predetermined threshold value, the system controller provides a next response to the request that indicates to any requesting processors that the requesting processor should utilize super-coherent data which is currently within its local cache. Similar operation on the address bus permits the system controller to triggering the issuing of Z1 Read requests for modified data in a shared cache line by processors which still have super-coherent data. The method also comprises enabling a load instruction with a plurality of bits that (1) indicates whether a resulting load request may receive super-coherent data and (2) overrides a coherency state indicating utilization of super-coherent data when said plurality of bits indicates that said load request may not utilize said super-coherent data. Specialized store instructions with appended bits and related functionality are also provided.
摘要翻译： 一种用于在多处理器数据处理系统中提高性能优化的方法。 在系统控制器逻辑中提供多个预定阈值，并用于触发特定带宽利用响应。 监视地址总线和数据总线带宽利用率。 响应于低于第一预定阈值的百分比的数据总线带宽利用率的下降，系统控制器在具有高速缓存行的窥探处理器处提供对高速缓存行的请求的特定响应，其中响应向请求处理器指示 将提供缓存行。 相反，如果数据总线带宽利用率的百分比上升到高于第二预定阈值，则系统控制器向请求处理器提供对请求的下一个响应，该请求指示请求处理器应该利用当前在其本地内的超相干数据 缓存。 地址总线上的类似操作允许系统控制器通过仍具有超相干数据的处理器触发在共享高速缓存行中发出对于修改数据的Z1读请求。 该方法还包括启用具有多个位的加载指令，其中（1）指示所产生的加载请求是否可以接收超相干数据，以及（2）当所述多个比特指示时，超过表示超相干数据的利用的相关性状态 所述加载请求可能不利用所述超相干数据。 还提供了具有附加位和相关功能的专用存储指令。
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63.发明授权Apparatus and method of layering cache and architectural specific functions to permit generic interface definition 失效分层缓存和架构特定功能以允许通用接口定义的装置和方法
公开(公告)号：US6122691A
公开(公告)日：2000-09-19
申请号：US224105
申请日：1999-01-04
CPC分类号： G06F12/0897 , G06F12/0893 , G06F13/1694
摘要： Cache and architectural functions within a cache controller are layered and provided with generic interfaces. Layering cache and architectural operations allows the definition of generic interfaces between controller logic and bus interface units within the controller. The generic interfaces are defined by extracting the essence of supported operations into a generic protocol. The interfaces themselves may be pulsed or held interfaces, depending on the character of the operation. Because the controller logic is isolated from the specific protocols required by a processor or bus architecture, the design may be directly transferred to new controllers for different protocols or processors by modifying the bus interface units appropriately.
摘要翻译： 高速缓存控制器中的缓存和架构功能是分层的，并具有通用接口。 分层缓存和架构操作允许在控制器内的控制器逻辑和总线接口单元之间定义通用接口。 通用接口通过将支持的操作的本质提取到通用协议中来定义。 接口本身可以是脉冲或保持的接口，这取决于操作的特性。 由于控制器逻辑与处理器或总线架构所需的特定协议隔离，所以可以通过适当地修改总线接口单元将设计直接传送到不同协议或处理器的新控制器。
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64.发明授权Method of layering cache and architectural specific functions to promote operation symmetry 失效分层缓存和架构特定功能的方法，以促进操作对称
公开(公告)号：US6061755A
公开(公告)日：2000-05-09
申请号：US839441
申请日：1997-04-14
CPC分类号： G06F12/0831
摘要： Cache and architectural functions within a cache controller are layered so that architectural operations may be symmetrically treated regardless of whether initiated by a local processor or by a horizontal processor. The same cache controller logic which handles architectural operations initiated by a horizontal device also handles architectural operations initiated by a local processor. Architectural operations initiated by a local processor are passed to the system bus and self-snooped by the controller. If necessary, the architectural controller changes the operation protocol to conform to the system bus architecture.
摘要翻译： 高速缓存控制器内的缓存和架构功能被分层，使得架构操作可以被对称地处理，而不管是由本地处理器还是由水平处理器启动。 处理由水平设备发起的架构操作的相同缓存控制器逻辑也处理由本地处理器启动的架构操作。 由本地处理器启动的架构操作被传递给系统总线，并由控制器自行侦测。 如果需要，架构控制器改变操作协议以符合系统总线体系结构。
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65.发明授权
公开(公告)号：US5951668A
公开(公告)日：1999-09-14
申请号：US934407
申请日：1997-09-19
CPC分类号： G06F13/4013 , G06F13/36
摘要： A method and apparatus for ordering operations and data received by a first bus having a first ordering policy according to a second ordering policy which is different from the first ordering policy, and for transferring the ordered data on a second bus having the second ordering policy. The system includes a plurality of execution units for storing operations and executing the transfer of data between the first and second buses. Each one of the execution units are assigned to a group which represent a class of operations. The apparatus further includes intra prioritizing means, for each group, for prioritizing the stored operations according to the second ordering policy exclusive of the operation stored in the other group. The system also includes inter prioritizing means for determining which one of the prioritized operations can proceed to execute according to the second ordering policy.
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66.发明授权Method and system for controlling access to a shared resource in a data processing system utilizing pseudo-random priorities 失效用于利用伪随机优先级来控制对数据处理系统中的共享资源的访问的方法和系统
公开(公告)号：US5935234A
公开(公告)日：1999-08-10
申请号：US839436
申请日：1997-04-14
IPC分类号： G06F15/16 , G06F13/364 , G06F15/177 , G06F13/14
CPC分类号： G06F13/364
摘要： A method and system for controlling access to a shared resource in a data processing system are described. According to the method, a number of requests for access to the resource are generated by a number of requesters that share the resource. Each of the requesters is assigned a current priority, at least the highest current priority being determined substantially randomly with respect to previous priorities of the requestors. In response to the current priorities of the requestors, a request for access to the resource is granted. In one embodiment, a requester corresponding to a granted request is signaled that its request has been granted, and a requester corresponding to a rejected request is signaled that its request was not granted.
摘要翻译： 描述了用于控制对数据处理系统中的共享资源的访问的方法和系统。 根据该方法，通过共享资源的多个请求者生成对资源的访问的多个请求。 每个请求者被分配当前优先级，至少最高当前优先级相对于请求者的先前优先级基本随机地确定。 响应请求者的当前优先级，授予访问该资源的请求。 在一个实施例中，与被许可的请求相对应的请求者用信号通知其请求已经被许可，并且与被拒绝的请求相对应的请求者用信号通知其请求未被授予。
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67.发明授权Apparatus and method for separately layering cache and architectural specific functions in different operational controllers to facilitate design extension 失效用于在不同的操作控制器中单独分层缓存和架构特定功能以便于设计扩展的装置和方法
公开(公告)号：US5909561A
公开(公告)日：1999-06-01
申请号：US839443
申请日：1997-04-14
CPC分类号： G06F12/0888
摘要： Cache and architectural functions within a cache controller are layered and provided with generic interfaces, isolating controller logic from specific architectural complexities. Controller logic may thus be readily duplicated to extend a nonshared cache controller design to a shared cache controller design, with only straightforward modifications required. Throttling of processor-initiated operations handled by the same controller logic resolves operation flow rate issues with acceptable performance trade-offs.
摘要翻译： 高速缓存控制器中的缓存和架构功能分层并提供通用接口，将控制器逻辑与特定架构复杂性隔离开来。 因此，控制器逻辑可以容易地重复，以将非共享高速缓存控制器设计扩展到共享高速缓存控制器设计，只需要直接的修改。 由同一控制器逻辑处理的由处理器启动的操作的调节可以解决具有可接受的性能权衡的操作流速问题。
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68.发明授权
公开(公告)号：US5996049A
公开(公告)日：1999-11-30
申请号：US839548
申请日：1997-04-14
CPC分类号： G06F12/0831
摘要： A method of providing instructions and data values to a processing unit in a multi-processor computer system, by expanding the prior-art MESI cache-coherency protocol to include an additional cache-entry state corresponding to a most recently accessed state. Each cache of the processing units has at least one cache line with a block for storing the instruction or data value, and an indication is provided that a cache line having a block which contains the instruction or data value is in a "recently read" state. Each cache entry has three bits to indicate the current state of the cache entry (one of five possible states). A processing unit which desires to access a shared instruction or data value detects transmission of the indication from the cache having the most recently accessed copy, and the instruction or data value is sourced from this cache. Upon sourcing the instruction or data value, the cache that originally contained the most recently accessed copy thereof changes its indication to indicate that its copy is now shared, and the processing unit which accessed the instruction or data value is thereafter indicated as having the cache containing the copy thereof that was most recently accessed. This protocol allows instructions and data values which are shared among several caches to be sourced directly (intervened) by the cache having the most recently accessed copy, without retrieval from system memory (RAM), significantly improving the processing speed of the computer system.
摘要翻译： 通过扩展现有技术的MESI高速缓存一致性协议以包括对应于最近访问状态的附加高速缓存入口状态，向多处理器计算机系统中的处理单元提供指令和数据值的方法。 处理单元的每个高速缓存具有至少一个具有用于存储指令或数据值的块的高速缓存行，并且提供了具有包含指令或数据值的块的高速缓存行处于“最近读取”状态的指示 。 每个缓存条目有三个位用于指示缓存条目的当前状态（五种可能状态之一）。 期望访问共享指令或数据值的处理单元检测来自具有最近访问的副本的高速缓存的指示的传输，并且指令或数据值来自该高速缓存。 在提供指令或数据值时，最初包含其最近访问的副本的高速缓存改变其指示以指示其副本现在被共享，并且访问该指令或数据值的处理单元此后被指示为具有高速缓存 最近访问的副本。 该协议允许由具有最近访问的副本的缓存直接（介入）在几个高速缓存之间共享的指令和数据值，而不从系统存储器（RAM）检索，显着地提高了计算机系统的处理速度。
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公开(公告)号：US5771247A
公开(公告)日：1998-06-23
申请号：US611439
申请日：1996-03-04
IPC分类号： G06F11/10
CPC分类号： G06F11/1044 , G06F11/10 , G06F11/1024
摘要： A system and method are provided that use a determination of bad data parity and the state of an error signal (Derr.sub.--) as a functional signal indicating a specific type of error in a particular system component. If the Derr.sub.-- signal is active, the parity error recognized by the CPU was caused by a correctable condition in a data providing device. In this instance, the processor will read the corrected data from a buffer without reissuing a fetch request. When the CPU finds a parity error, but Derr.sub.-- is not active a more serious fault condition is identified (bus error or uncorrectable multibit error) requiring a machine level interrupt, or the like. And, when no parity is found by the CPU and Derr.sub.-- is not active, then the data is known to be valid and the parity/ECC latency is eliminated, thereby saving processing cycle time.
摘要翻译： 提供一种系统和方法，其使用错误数据奇偶校验的确定和误差信号（Derr-）的状态作为指示特定系统组件中的特定类型的错误的功能信号。 如果Derr信号有效，则由CPU识别的奇偶校验错误是由数据提供设备中的可纠正条件引起的。 在这种情况下，处理器将从缓冲区读取校正的数据，而不重新发出读取请求。 当CPU发现奇偶校验错误，但是Derr不活动时，识别出需要机器级别中断的更严重的故障状况（总线错误或不可校正的多位错误）等。 而且，当CPU没有找到奇偶校验，并且Derr-没有激活时，数据被认为是有效的，并且奇偶校验/ ECC等待时间被消除，从而节省处理周期时间。
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公开(公告)号：US6029217A
公开(公告)日：2000-02-22
申请号：US317006
申请日：1994-10-03
IPC分类号： G06F15/16 , G06F13/362 , G06F13/364 , G06F15/177 , G06F13/20
CPC分类号： G06F13/364
摘要： A queued arbitration mechanism transfers all queued processor bus requests to a centralized system controller/arbiter in a descriptive and pipelined manner. Transferring these descriptive and pipelined bus requests to the system controller allows the system controller to optimize the system bus utilization via prioritization of all of the requested bus operations and pipelining appropriate bus grants. Intelligent bus request information is transferred to the system controller via encoding and serialization techniques.
摘要翻译： 排队的仲裁机制将所有排队的处理器总线请求以描述和流水线方式传送到集中式系统控制器/仲裁器。 将这些描述性和流水线总线请求传送到系统控制器允许系统控制器通过对所有所请求的总线操作和流水线适当的总线授权的优先级来优化系统总线利用率。 智能总线请求信息通过编码和串行化技术传输到系统控制器。
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