公开(公告)号：US07482891B2

公开(公告)日：2009-01-27

申请号：US11822652

申请日：2007-07-09

Applicant: Jan R. Westra ,  Jan Mulder ,  Franciscus Maria Leonardus van der Goes

Inventor： Jan R. Westra ,  Jan Mulder ,  Franciscus Maria Leonardus van der Goes

IPC: H03H7/24

CPC classification number: H03H11/245 ,  H03H7/24

Abstract: A programmable gain attenuator includes a termination resistor. A first termination switch connects one side of the termination resistor to a first output. A second termination switch connects another side of the termination resistor to a second output. A first resistor ladder is arranged between a first input and the first side of the termination resistor. A first plurality of switches connect a corresponding tap from the first resistor ladder to the first output. A second resistor ladder is arranged between a second input and the second side of the termination resistor. A second plurality of switches connect a corresponding tap from the second resistor ladder to the second output. A first switch of the first plurality of switches is turned on, followed by a second switch of first plurality of switches turned off, followed by a third switch of first plurality of switches turned on. A first switch of the second plurality of switches is turned on, followed by a second switch of second plurality of switches turned off, followed by a third switch of second plurality of switches turned on.

Abstract translation: 可编程增益衰减器包括终端电阻。 第一终端开关将终端电阻器的一侧连接到第一输出。 第二终端开关将终端电阻器的另一侧连接到第二输出端。 在第一输入和终端电阻的第一侧之间布置第一电阻梯。 第一多个开关将来自第一电阻梯的相应抽头连接到第一输出。 在第二输入端和终端电阻器的第二侧之间布置第二电阻梯。 第二多个开关将来自第二电阻梯的相应抽头连接到第二输出。 第一多个开关的第一开关被接通，接着是第一多个开关的第二开关被关闭，随后开启第一组开关的第三开关。 第二多个开关的第一开关被接通，随后是第二多个开关的第二开关被关闭，随后是第二多个开关的第三开关导通。

公开(公告)号：US07423569B2

公开(公告)日：2008-09-09

申请号：US11409277

申请日：2006-04-24

Applicant: Yee Ling Cheung ,  Kevin T. Chan ,  Jan Mulder

Inventor： Yee Ling Cheung ,  Kevin T. Chan ,  Jan Mulder

IPC: H03M1/66

CPC classification number: H03F3/45183 ,  H03F2203/45466

Abstract: Provided is a method and system for controlling current characteristics in a transceiver having a transmitter. The method includes identifying a phase control signal from an adjacent current cell preceding the particular current cell in time and logically ORing the phase control signal from the preceding cell with a phase control signal from the particular current cell.

Abstract translation: 提供了一种用于控制具有发射机的收发机中的电流特性的方法和系统。 该方法包括在时间上识别来自特定当前小区之前的相邻当前小区的相位控制信号，并且将来自前一小区的相位控制信号与来自特定当前小区的相位控制信号进行逻辑或运算。

公开(公告)号：US20070296456A1

公开(公告)日：2007-12-27

申请号：US11798334

申请日：2007-05-11

Applicant: Frank van der GOES ,  Christopher Ward ,  Jan Mulder ,  Ovidiu Bajdechi

Inventor： Frank van der GOES ,  Christopher Ward ,  Jan Mulder ,  Ovidiu Bajdechi

IPC: H03K17/16

CPC classification number: H03K3/012 ,  H03K19/0005 ,  H04L25/0278

Abstract: An electrical circuit comprising a line driver for providing Ethernet signals is disclosed. The line driver comprises a voltage mode line driver for producing 1000BT and 100BT Ethernet signals and an active output impedance line driver arranged parallel to the voltage mode line driver. The line driver is capable of producing 1000BT or 100BT or 10BT Ethernet signals, wherein either the voltage mode line driver or the active impedance line driver is active.

Abstract translation: 公开了一种包括用于提供以太网信号的线路驱动器的电路。 线路驱动器包括用于产生1000BT和100BT以太网信号的电压模式线路驱动器和与电压模式线路驱动器并联布置的有源输出阻抗线路驱动器。 线路驱动器能够产生1000BT或100BT或10BT以太网信号，其中电压模式线路驱动器或有源阻抗线路驱动器是活动的。

公开(公告)号：US07242267B2

公开(公告)日：2007-07-10

申请号：US10830112

申请日：2004-04-23

Applicant: Jan R. Westra ,  Jan Mulder ,  Franciscus Maria Leonardus van der Goes

Inventor： Jan R. Westra ,  Jan Mulder ,  Franciscus Maria Leonardus van der Goes

IPC: H03H7/24

CPC classification number: H03H11/245 ,  H03H7/24

Abstract: A programmable gain attenuator includes a termination resistor. A first termination switch connects one side of the termination resistor to a first output. A second termination switch connects another side of the termination resistor to a second output. A first resistor ladder is arranged between a first input and the first side of the termination resistor. A first plurality of switches connect a corresponding tap from the first resistor ladder to the first output. A second resistor ladder is arranged between a second input and the second side of the termination resistor. A second plurality of switches connect a corresponding tap from the second resistor ladder to the second output. A first switch of the first plurality of switches is turned on, followed by a second switch of first plurality of switches turned off, followed by a third switch of first plurality of switches turned on. A first switch of the second plurality of switches is turned on, followed by a second switch of second plurality of switches turned off, followed by a third switch of second plurality of switches turned on.

Abstract translation: 可编程增益衰减器包括终端电阻。 第一终端开关将终端电阻器的一侧连接到第一输出。 第二终端开关将终端电阻器的另一侧连接到第二输出端。 在第一输入和终端电阻的第一侧之间布置第一电阻梯。 第一多个开关将来自第一电阻梯的相应抽头连接到第一输出。 在第二输入端和终端电阻器的第二侧之间布置第二电阻梯。 第二多个开关将来自第二电阻梯的相应抽头连接到第二输出。 第一多个开关的第一开关被接通，接着是第一多个开关的第二开关被关闭，随后开启第一组开关的第三开关。 第二多个开关的第一开关被接通，随后是第二多个开关的第二开关被关闭，随后是第二多个开关的第三开关导通。

公开(公告)号：US07190298B2

公开(公告)日：2007-03-13

申请号：US11084236

申请日：2005-03-21

Applicant: Jan Mulder

Inventor： Jan Mulder

IPC: H03M1/12

CPC classification number: H03K17/04106 ,  H03F3/45183 ,  H03F3/45632 ,  H03F2203/45352 ,  H03F2203/45354 ,  H03F2203/45511 ,  H03M1/204 ,  H03M1/365

Abstract: An analog to digital converter includes a resistive ladder outputting a plurality of reference voltages and a coarse ADC receiving the reference voltages and a voltage input. A plurality of coarse comparators receive an output of the coarse ADC. A switch matrix receives an output of the coarse ADC and the reference voltages. The switch matrix inputs a plurality of control signals for selecting at least two voltage subranges. A fine ADC receives the two voltage subranges and the voltage input. A plurality of fine comparators receive an output of the fine ADC. An encoder converts outputs of the coarse and fine comparators to a digital representation of the voltage input. The voltage subranges are adjacent. Each control signal includes a plurality of control lines for controlling corresponding switches. The switches are field effect transistors.

公开(公告)号：US20060164125A1

公开(公告)日：2006-07-27

申请号：US11038386

申请日：2005-01-21

Applicant: Jan Mulder

Inventor： Jan Mulder

IPC: G01R19/00

CPC classification number: G01R19/16519 ,  G01R19/16557 ,  H03F3/45183 ,  H03F3/45632 ,  H03F2200/78 ,  H03F2203/45366 ,  H03F2203/45644 ,  H03M1/0607

Abstract: A differential comparator with reduced offset. The differential comparator includes a first transistor coupled to a first input current and a second transistor coupled to a second input current. The first and second transistors are biased as diodes during a reset phase to store an offset voltage on parasitic capacitances of the first and second transistors. The first and second transistors are connected together as a latch to provide an output during a latch phase. Drain currents of the first and the second transistors substantially equal the first and the second input currents, respectively, during the reset phase and at the beginning of the latch phase. During the latch phase, currents approximately twice as large as differential-mode signal currents provided by the first and the second input currents are provided to the first and the second transistors, respectively.

Abstract translation: 具有减小偏移的差分比较器。 差分比较器包括耦合到第一输入电流的第一晶体管和耦合到第二输入电流的第二晶体管。 第一和第二晶体管在复位阶段被偏置为二极管，以便在第一和第二晶体管的寄生电容上存储偏移电压。 第一和第二晶体管作为锁存器连接在一起以在锁存相位期间提供输出。 第一和第二晶体管的漏极电流分别在复位阶段期间和锁存相位开始时基本上等于第一和第二输入电流。 在锁存阶段期间，分别向第一和第二晶体管提供大约是由第一和第二输入电流提供的差分模式信号电流的两倍的电流。

公开(公告)号：US07019679B2

公开(公告)日：2006-03-28

申请号：US10953420

申请日：2004-09-30

Applicant: Jan Mulder ,  Franciscus Maria Leonardus van der Goes

Inventor： Jan Mulder ,  Franciscus Maria Leonardus van der Goes

IPC: H03M1/34

CPC classification number: H03K17/002 ,  H03K17/145 ,  H03M1/36 ,  H03M1/365

Abstract: A differential multiplexer includes a plurality of multiplexing circuits. Each multiplexing circuit inputs a corresponding differential input signal including a positive input signal and a negative input signal, and outputs positive and negative output signals. Each multiplexing circuit includes first, second, third and fourth transistors. The first and second transistors input the positive input signal. The third and fourth transistors input the negative input signal. Outputs of the first and third transistors are connected to the positive output signal. Outputs of the second and fourth transistors are connected to the negative output signal. The positive and negative output signals are controlled using gate voltages on the first and fourth transistors. The second and third transistors are turned off when the differential multiplexer is in use. The transistors are cross-coupled to make leakage between the positive and negative input signals common mode in the positive and negative output signals.

Abstract translation: 差分多路复用器包括多个复用电路。 每个复用电路输入包括正输入信号和负输入信号的对应差分输入信号，并输出正和负输出信号。 每个复用电路包括第一，第二，第三和第四晶体管。 第一和第二晶体管输入正输入信号。 第三和第四晶体管输入负输入信号。 第一和第三晶体管的输出端连接到正输出信号。 第二和第四晶体管的输出端连接到负输出信号。 正和负输出信号通过第一和第四晶体管上的栅极电压来控制。 当使用差分多路复用器时，第二和第三晶体管截止。 晶体管交叉耦合以在正输入信号和负输出信号中的正输入信号和负输入信号共模之间产生泄漏。

公开(公告)号：US20050093644A1

公开(公告)日：2005-05-05

申请号：US10830112

申请日：2004-04-23

Applicant: Jan Westra ,  Jan Mulder ,  Franciscus van der Goes

Inventor： Jan Westra ,  Jan Mulder ,  Franciscus van der Goes

IPC: H01P1/22 ,  H03H7/24

CPC classification number: H03H11/245 ,  H03H7/24

Abstract: A programmable gain attenuator includes a termination resistor. A first termination switch connects one side of the termination resistor to a first output. A second termination switch connects another side of the termination resistor to a second output. A first resistor ladder is arranged between a first input and the first side of the termination resistor. A first plurality of switches connect a corresponding tap from the first resistor ladder to the first output. A second resistor ladder is arranged between a second input and the second side of the termination resistor. A second plurality of switches connect a corresponding tap from the second resistor ladder to the second output. A first switch of the first plurality of switches is turned on, followed by a second switch of first plurality of switches turned off, followed by a third switch of first plurality of switches turned on. A first switch of the second plurality of switches is turned on, followed by a second switch of second plurality of switches turned off, followed by a third switch of second plurality of switches turned on.

公开(公告)号：US06867621B2

公开(公告)日：2005-03-15

申请号：US10720144

申请日：2003-11-25

Applicant: Jan Mulder ,  Yee Ling Cheung

Inventor： Jan Mulder ,  Yee Ling Cheung

IPC: H03K17/041 ,  H03M1/06 ,  H03M1/08 ,  H03M1/14 ,  H03M1/20 ,  H03M1/36 ,  H04L25/02 ,  H03K5/22

CPC classification number: H03K17/04106 ,  H03M1/146 ,  H03M1/204 ,  H03M1/365 ,  H03M1/742 ,  H04L25/026 ,  H04L25/0276

Abstract: A differential line driver includes first, second, third and fourth cascode transistors connected in parallel, wherein drains of the first and third transistors are connected to a negative output of the differential line driver, and wherein drains of the second and fourth transistors are connected to a positive output of the differential line driver. First, second, third and fourth switching transistors are connected in series with corresponding first, second, third and fourth cascode transistors and driven by a data signal. First and second compound transistors inputting a class AB operation signal at their gates, wherein the first compound transistor is connected to sources of the first and second switching transistors, and wherein the second compound transistor is connected to sources of the third and fourth switching transistors.

Abstract translation: 差分线路驱动器包括并联连接的第一，第二，第三和第四共源共栅晶体管，其中第一和第三晶体管的漏极连接到差分线路驱动器的负输出，并且其中第二和第四晶体管的漏极连接到 差分线路驱动器的正输出。 第一，第二，第三和第四开关晶体管与对应的第一，第二，第三和第四共源共栅晶体管串联连接并由数据信号驱动。 第一和第二复合晶体管在其栅极处输入AB类操作信号，其中第一复合晶体管连接到第一和第二开关晶体管的源极，并且其中第二复合晶体管连接到第三和第四开关晶体管的源极。

公开(公告)号：US06831585B2

公开(公告)日：2004-12-14

申请号：US10684444

申请日：2003-10-15

Applicant: Jan Mulder ,  Christopher Michael Ward

Inventor： Jan Mulder ,  Christopher Michael Ward

IPC: H03M112

CPC classification number: H03K17/04106 ,  H03M1/0646 ,  H03M1/146 ,  H03M1/204 ,  H03M1/206 ,  H03M1/361 ,  H03M1/365

Abstract: An analog to digital converter includes a first amplifier array connected to taps from a reference ladder, a second amplifier array, wherein each amplifier in the first amplifier array is connected to only two amplifiers of the second amplifier array, a third amplifier array, wherein each amplifier in the second amplifier array is connected to only two amplifiers of the third amplifier array, and an encoder connected to outputs of the third amplifier array that converts the outputs to an N-bit digital signal.

Abstract translation: 模数转换器包括连接到参考梯形图的抽头的第一放大器阵列，第二放大器阵列，其中第一放大器阵列中的每个放大器仅连接到第二放大器阵列的两个放大器，第三放大器阵列，其中每个 第二放大器阵列中的放大器仅连接到第三放大器阵列的两个放大器，以及连接到第三放大器阵列的输出的编码器，其将输出转换为N位数字信号。