公开(公告)号：US10541038B2

公开(公告)日：2020-01-21

申请号：US16205165

申请日：2018-11-29

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Xiang Yang ,  Zhenming Zhou ,  Deepanshu Dutta ,  Huai-Yuan Tseng

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/04 ,  G11C16/32 ,  G11C11/56

Abstract: An apparatus, system, and method are disclosed for identifying and selecting a subgroup of memory cells for use during a programming or erasing operation, in order to execute the programming or erasing operation in less time, while avoiding over and under programming errors. Memory devices disclosed herein may include a state change/programming circuit, a counting circuit, a determination circuit, an identification circuit, and/or a subgroup selection circuit, where each of these circuits are configured to perform operations related to the overall process of identifying and selecting the subgroup of memory cells for utilization during a programming operation.

公开(公告)号：US10541037B2

公开(公告)日：2020-01-21

申请号：US16002793

申请日：2018-06-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Dengtao Zhao ,  Deepanshu Dutta

IPC: G11C16/34 ,  G11C8/08 ,  G11C16/04 ,  G11C7/04 ,  G11C16/12

Abstract: Program disturb is a condition that includes the unintended programming of a memory cell while performing a programming process for other memory cells. Such unintended programming can cause an error in the data being stored. In some cases, program disturb can result from electrons trapped in the channel being accelerated from one side of a selected word line to another side of the selected word line and redirected into the selected word line. To prevent such program disturb, it is proposed to open the channel from one side of a selected word line to the other side of the selected word line after a sensing operation for program verify and prior to a subsequent programming voltage being applied.

公开(公告)号：US20190392909A1

公开(公告)日：2019-12-26

申请号：US16014850

申请日：2018-06-21

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G11C16/34 ,  G11C16/10

Abstract: A circuit includes a program controller configured to perform a program operation with interleaved program-verify loops to program memory cells in a same block. During each program-verify loop, a control gate line voltage supply circuit first supplies a program pulse to a first cell of the block and then, before verifying the first cell, supplies a program pulse to a second cell of the block. After the program pulses are sent, the control gate line supply circuit consecutively supplies verify pulses to the first cell and the second cell such that a delay is introduced between the respective program and verify stages of the first and second cells. Additionally, a constant voltage bias on common control gate lines of the first and second memory cells is applied during the consecutive verify stages. Further, an order of verify pulses may be applied in a reverse order during a verify stage.

公开(公告)号：US20190392894A1

公开(公告)日：2019-12-26

申请号：US16019141

申请日：2018-06-26

Applicant: SanDisk Technologies LLC

Inventor： Dengtao Zhao ,  Deepanshu Dutta ,  Zhenming Zhou

IPC: G11C11/56 ,  G11C16/26 ,  G11C16/24 ,  G11C16/34 ,  H01L27/11556 ,  G11C16/04 ,  G11C16/30 ,  H01L27/11582

Abstract: A memory system includes a sense system configured to control parasitic noise sources by increasing selected bit line or channel voltages during sense stages. The increase may be tied to a triggering threshold voltage level. That is, while performing a memory operation, the sense system may increase the selected bit line voltage level dependent on a reference voltage level or memory state associated with a sense stage being above the triggering threshold level.

公开(公告)号：US20190392893A1

公开(公告)日：2019-12-26

申请号：US16019456

申请日：2018-06-26

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Dengtao Zhao ,  Huai-Yuan Tseng ,  Deepanshu Dutta ,  Zhongguang Xu ,  Yanli Zhang ,  Jin Liu

IPC: G11C11/56 ,  G11C16/24 ,  G11C16/08 ,  G11C16/14 ,  G11C16/34 ,  G11C16/04

Abstract: Non-volatile memory strings may include multiple selection devices for coupling memory cell devices to a bit line. Different programming operations may be used to program various individual selection devices in a non-volatile memory cells string. For example, a control circuit may set a threshold voltage of a particular selection device to a value greater than a threshold voltage of another selection device. In another example, the control circuit may program the selection device using an initial sense time. Subsequent to programming the selection device using the initial sense time, the control circuit may program the selection device using a different sense time that is shorter than the initial sense time.

公开(公告)号：US20190378581A1

公开(公告)日：2019-12-12

申请号：US16002836

申请日：2018-06-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Dengtao Zhao ,  Peng Zhang ,  Nan Lu ,  Deepanshu Dutta

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/08 ,  G11C16/04 ,  H01L27/11582 ,  H01L27/1157

Abstract: Program disturb is a condition that includes the unintended programming of a memory cell while performing a programming process for other memory cells. Such unintended programming can cause an error in the data being stored. In some cases, program disturb can result from electrons trapped in the channel being accelerated from one side of a selected word line to another side of the selected word line and redirected into the selected word line. To prevent such program disturb, it is proposed to open the channel from one side of a selected word line to the other side of the selected word line after a sensing operation for program verify and prior to a subsequent programming voltage being applied.

公开(公告)号：US10482984B2

公开(公告)日：2019-11-19

申请号：US15952752

申请日：2018-04-13

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G11C16/34 ,  H01L27/11556 ,  H01L27/11582 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

Abstract: Apparatuses and techniques are described for optimizing a program operation in a memory device. A storage location stores programing data for each word line, such as a program voltage for a set of memory cells. The set of memory cells may be periodically evaluated to determine updated programming setting(s). In one approach, the evaluation involves repeatedly sensing the set of memory cells between a program pulse and a verify signal in a program loop. The word line voltage can be stepped down to an intermediate voltage, then ramped down at a controlled rate while repeatedly sensing the memory cells, such as to detect an upper or lower tail of a threshold voltage distribution. The position of the tail can indicate a degree of over programming and this information can be used to adjust the programming setting(s) in a subsequent program operation.

公开(公告)号：US20190295669A1

公开(公告)日：2019-09-26

申请号：US15928976

申请日：2018-03-22

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Piyush Dak ,  Wei Zhao ,  Huai-Yuan Tseng ,  Deepanshu Dutta ,  Mohan Dunga

IPC: G11C16/34 ,  G11C16/32 ,  G11C16/26 ,  G11C16/10

Abstract: A circuit includes a detection circuit configured to determine a capacitance delay (RC-delay) in an initial stage of a read or program operation and to adjust timing for detecting data in a subsequent stage, or portion of a stage, of the same read or programing operation. In particular, during a program operation a detection circuit may be configured to detect a pre-charge time for a bit line and adjust a timing of subsequent verify stages of the bit line during the same program operation based on the detected pre-charge time. Additionally, a word line circuit may be configured to detect a pre-charge time for a word line during an initial stage of a read operation and adjust read timing for a subsequent portion of the same read stage, or subsequent read stage of the read operation based on the detected word line pre-charge time.

公开(公告)号：US10381083B1

公开(公告)日：2019-08-13

申请号：US16018018

申请日：2018-06-25

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Kun-Huan Shih ,  Matthias Baenninger ,  Huai-Yuan Tseng ,  Dengtao Zhao ,  Deepanshu Dutta

IPC: G11C11/34 ,  G11C16/14 ,  G11C16/24 ,  G11C16/30 ,  G11C16/08 ,  G11C16/34 ,  H01L27/1157 ,  G11C16/04 ,  H01L27/11524

Abstract: A memory device and associated techniques avoid a disturb of a select gate transistor during an erase operation for memory cells in a string. During the erase operation, a channel potential gradient near the select gate transistors is reduced when the voltages of the bit line and the substrate are suitably controlled. In one approach, the voltage of the substrate at a source end of the memory string is increased to an intermediate level first before being increased to the erase voltage threshold level while the voltage of the bit line is held at a reference voltage level to delay floating the voltage of the bit line. Another approach builds off the first approach by temporarily decreasing the voltage of the bit line to a negative level before letting the voltage of the bit line to float at the same time as the voltage of the substrate is increased to the erase voltage threshold level.

公开(公告)号：US10229744B2

公开(公告)日：2019-03-12

申请号：US15816546

申请日：2017-11-17

Applicant: SanDisk Technologies LLC

Inventor： Deepanshu Dutta ,  Idan Alrod ,  Huai-Yuan Tseng ,  Amul Desai ,  Jun Wan ,  Ken Cheah ,  Sarath Puthenthermadam

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/26 ,  G11C16/16 ,  G11C8/08 ,  G11C16/08 ,  G11C29/02 ,  G11C11/56 ,  G11C29/12

Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of the memory cells can shift depending on the coupled up state of the word lines. In one approach, for a read operation, a representative word line voltage in a block is detected and a corresponding set of read voltages is selected. In another approach, a pre-read voltage pulse is applied to a selected word line in response to a read command, just prior to reading the selected cells. In another approach, a voltage pulse is periodically applied to each word line in a block to provide the word lines in a coupled up state. In another approach, a soft erase is performed after a read operation to prevent coupling up of the word lines.