公开(公告)号：US20210044283A1

公开(公告)日：2021-02-11

申请号：US16831452

申请日：2020-03-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JONGKYU RYU ,  Minsu Kim ,  Ahreum Kim ,  Daeseong Lee ,  Hyun Lee

IPC: H03K3/356 ,  H03K19/20 ,  H03K3/012

Abstract: A semi-dynamic flip-flop includes a semiconductor substrate, first through fourth power rails, and at least one clock gate line. The first through fourth power rails are disposed on the semiconductor substrate, extend in a first direction, and are arranged sequentially in a second direction substantially perpendicular to the first direction. The at least one clock gate line is disposed on the semiconductor substrate, and extends in the second direction to pass through at least two regions among a first region between the first power rail and the second power rail, a second region between the second power rail and the third power rail, and a third region between the third power rail and the fourth power rail. The at least one clock gate line receives an input clock signal.

公开(公告)号：US10673420B2

公开(公告)日：2020-06-02

申请号：US15981415

申请日：2018-05-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun Lee ,  Dae Seong Lee ,  Minsu Kim ,  Ahreum Kim ,  Chunghee Kim

IPC: H03K3/037 ,  H03K19/20 ,  G06F1/10 ,  G01R31/317 ,  G01R31/3177

Abstract: An electronic circuit includes a first flip-flop, a second flip-flop, and a clock generator. The first flip-flop comprises a first master latch and a first slave latch arranged in order along a first direction. The second flip-flop comprises a second master latch and a second slave latch arranged in order along a second direction that is opposite to the first direction. The clock generator is arranged between the first master latch and the second master latch and outputs a clock.

公开(公告)号：US10320369B2

公开(公告)日：2019-06-11

申请号：US15903507

申请日：2018-02-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunchul Hwang ,  Minsu Kim

IPC: H03K19/20 ,  G11C19/28 ,  G11C27/02 ,  H03K3/356 ,  G11C11/4074 ,  G11C11/4076

Abstract: In a sequential circuit, a first stage is configured to charge a voltage of a first node in response to a clock, and to discharge the voltage of the first node in response to the clock, a voltage of a second node, and data; a second stage is configured to charge the voltage of the second node in response to the clock, and to discharge the voltage of the second node in response to the clock and a logic signal; a combinational logic is configured to generate the logic signal based on the voltage of the first node, the voltage of the second node, and the data; and a latch circuit is configured to latch the voltage of the second node in response to the clock.

公开(公告)号：US20190040567A1

公开(公告)日：2019-02-07

申请号：US16054792

申请日：2018-08-03

Applicant: Samsung Electronics Co., Ltd

Inventor： Masahiro Uetsuhara ,  Takehiero Nakanishi ,  Minsu Kim ,  Shigeki Hayashi ,  Shin Kagami ,  Tomoyuki Okuno ,  Toshihiro Kamii

IPC: D06F39/08 ,  D06F33/02 ,  D06F37/12 ,  D06F39/00 ,  D06F39/04

Abstract: Disclosed herein is a top load washing machine having excellent functions while saving water. The washing machine may include a housing having a drain path installed at the bottom, a water collecting tub supported on the housing in the inside of the housing, and a rotating tub rotating on a shaft extending vertically in the inside of the water collecting tub. The rotating tub may include an outlet opening to the lower portion of a body member that can store water independently from the water collecting tub. The water collecting tub may include a first drain hole opening to the inside space of the water collecting tub, and a second drain hole communicating with the outlet. The drain path may include a first path connected to the first drain hole, and a second path connected to the second drain hole.

公开(公告)号：US10014862B2

公开(公告)日：2018-07-03

申请号：US15660527

申请日：2017-07-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunchul Hwang ,  Minsu Kim

IPC: H03K19/00

CPC classification number: H03K19/0016 ,  G06F1/3237 ,  H03K19/0013 ,  Y02D10/128

Abstract: A clock gating circuit includes a first precharge unit charging a first node based on a clock signal, a second precharge unit charging a second node based on the clock signal, a first discharge unit discharging the first node based on the clock signal, a second discharge unit discharging the second node based on the clock signal, a first cross-coupled maintain unit maintaining the first node at a charge state according to a voltage level of the second node, a second cross-coupled maintain unit maintaining the second node at a charge state according to a voltage level of the first node, and a control unit controlling the first and second discharge units to discharge the first node or the second node on the basis of a clock enable signal.

公开(公告)号：US09762240B2

公开(公告)日：2017-09-12

申请号：US15153799

申请日：2016-05-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunchul Hwang ,  Minsu Kim

IPC: H03K19/00

CPC classification number: H03K19/0016 ,  G06F1/3237 ,  H03K19/0013

Abstract: A clock gating circuit includes a first precharge unit charging a first node based on a clock signal, a second precharge unit charging a second node based on the clock signal, a first discharge unit discharging the first node based on the clock signal, a second discharge unit discharging the second node based on the clock signal, a first cross-coupled maintain unit maintaining the first node at a charge state according to a voltage level of the second node, a second cross-coupled maintain unit maintaining the second node at a charge state according to a voltage level of the first node, and a control unit controlling the first and second discharge units to discharge the first node or the second node on the basis of a clock enable signal.

公开(公告)号：US09543026B2

公开(公告)日：2017-01-10

申请号：US14865275

申请日：2015-09-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Ho Song ,  Minsu Kim ,  Il-Han Park ,  Su Chang Jeon

IPC: G11C7/10 ,  G11C16/24 ,  G11C16/26

CPC classification number: G11C16/24 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3459 ,  G11C2207/005

Abstract: An operating method of a nonvolatile memory device is provided. The nonvolatile memory device includes first and second page buffers, and first and second bit lines connected thereto, respectively. First and second latch nodes of the first page buffer are charged to have a voltage having a first level according to data stored in a first latch of the first page buffer. After the charging of the first latch node is started, a sensing node of the second page buffer is pre-charged. The sensing node is connected to the second bit line. Data stored in the first latch is dumped into a second latch of the first page buffer during the pre-charging of the sensing node of the second page buffer.

Abstract translation: 提供了一种非易失性存储器件的操作方法。 非易失性存储器件分别包括第一和第二页缓冲器以及与其相连的第一和第二位线。 第一页缓冲器的第一和第二锁存节点被充电以具有根据存储在第一页缓冲器的第一锁存器中的数据具有第一电平的电压。 在第一锁存节点的充电开始之后，第二页缓冲器的感测节点被预充电。 感测节点连接到第二位线。 存储在第一锁存器中的数据在第二页缓冲器的感测节点的预充电期间被转储到第一页缓冲器的第二锁存器中。

公开(公告)号：US20160093388A1

公开(公告)日：2016-03-31

申请号：US14865275

申请日：2015-09-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNG-HO SONG ,  Minsu Kim ,  Il-Han Park ,  Su Chang Jeon

IPC: G11C16/24 ,  G11C16/32 ,  G11C16/26

CPC classification number: G11C16/24 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3459 ,  G11C2207/005

Abstract: An operating method of a nonvolatile memory device is provided. The nonvolatile memory device includes first and second page buffers, and first and second bit lines connected thereto, respectively. First and second latch nodes of the first page buffer are charged to have a voltage having a first level according to data stored in a first latch of the first page buffer. After the charging of the first latch node is started, a sensing node of the second page buffer is pre-charged. The sensing node is connected to the second bit line. Data stored in the first latch is dumped into a second latch of the first page buffer during the pre-charging of the sensing node of the second page buffer.

Abstract translation: 提供了一种非易失性存储器件的操作方法。 非易失性存储器件分别包括第一和第二页缓冲器以及与其相连的第一和第二位线。 第一页缓冲器的第一和第二锁存节点被充电以具有根据存储在第一页缓冲器的第一锁存器中的数据具有第一电平的电压。 在第一锁存节点的充电开始之后，第二页缓冲器的感测节点被预充电。 感测节点连接到第二位线。 存储在第一锁存器中的数据在第二页缓冲器的感测节点的预充电期间被转储到第一页缓冲器的第二锁存器中。