公开(公告)号：US11646736B2

公开(公告)日：2023-05-09

申请号：US17371544

申请日：2021-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nam Hee Lee ,  Ho Joon Kim ,  Jung-Ho Song

IPC: G11C16/08 ,  H03K19/0175 ,  G11C16/04 ,  G11C16/30 ,  G09G3/20

CPC classification number: H03K19/017509 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/30 ,  G09G3/20 ,  G09G2310/0289

Abstract: A semiconductor device includes a memory cell array including a plurality of memory blocks, a control logic, a level shifter configured to generate a first internal voltage and a second internal voltage lower than the first internal voltage using a received external voltage on the basis of a control signal from the control logic, and a row decoder configured to provide the first and second internal voltages generated by the level shifter to the memory cell array. The level shifter generates the first internal voltage using the external voltage, generates the second internal voltage using the generated first internal voltage in a power-up mode of the semiconductor device, and generates the second internal voltage using the external voltage in a standby mode of the semiconductor device.

公开(公告)号：US09543026B2

公开(公告)日：2017-01-10

申请号：US14865275

申请日：2015-09-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Ho Song ,  Minsu Kim ,  Il-Han Park ,  Su Chang Jeon

IPC: G11C7/10 ,  G11C16/24 ,  G11C16/26

CPC classification number: G11C16/24 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3459 ,  G11C2207/005

Abstract: An operating method of a nonvolatile memory device is provided. The nonvolatile memory device includes first and second page buffers, and first and second bit lines connected thereto, respectively. First and second latch nodes of the first page buffer are charged to have a voltage having a first level according to data stored in a first latch of the first page buffer. After the charging of the first latch node is started, a sensing node of the second page buffer is pre-charged. The sensing node is connected to the second bit line. Data stored in the first latch is dumped into a second latch of the first page buffer during the pre-charging of the sensing node of the second page buffer.

Abstract translation: 提供了一种非易失性存储器件的操作方法。 非易失性存储器件分别包括第一和第二页缓冲器以及与其相连的第一和第二位线。 第一页缓冲器的第一和第二锁存节点被充电以具有根据存储在第一页缓冲器的第一锁存器中的数据具有第一电平的电压。 在第一锁存节点的充电开始之后，第二页缓冲器的感测节点被预充电。 感测节点连接到第二位线。 存储在第一锁存器中的数据在第二页缓冲器的感测节点的预充电期间被转储到第一页缓冲器的第二锁存器中。

公开(公告)号：US10324629B2

公开(公告)日：2019-06-18

申请号：US15869769

申请日：2018-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Hoon Lee ,  Eun-Suk Cho ,  Woo-Pyo Jeong ,  Sang-Wan Nam ,  Jung-Ho Song ,  Yun-Ho Hong ,  Jae-Hoon Lee

IPC: G11C7/06 ,  G06F3/06 ,  H01L27/02 ,  H01L21/265 ,  G11C7/10 ,  G11C16/26 ,  G11C16/04 ,  G11C16/32 ,  H01L27/11582 ,  H01L27/11573

Abstract: A non-volatile memory device includes a memory cell array region in which memory cells are vertically stacked on a substrate and a page buffer region in which first and second page buffers are arranged. A first distance between the memory cell array region and the first page buffer is shorter than a second distance between the memory cell array region and the second page buffer. The first page buffer includes a first transistor driven in response to a first control signal. The second page buffer includes a second transistor driven in response to a second control signal corresponding to the first control signal. At least one of design constraints and processing constraints with respect to the first and second transistors is different.

公开(公告)号：US09947414B2

公开(公告)日：2018-04-17

申请号：US15377504

申请日：2016-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Ho Song ,  Minsu Kim ,  Il Han Park ,  Su Chang Jeon

IPC: G11C16/24 ,  G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/32 ,  G11C16/34

CPC classification number: G11C16/24 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3459 ,  G11C2207/005

Abstract: An operating method of a nonvolatile memory device is provided. The nonvolatile memory device includes first and second page buffers, and first and second bit lines connected thereto, respectively. First and second latch nodes of the first page buffer are charged to have a voltage having a first level according to data stored in a first latch of the first page buffer. After the charging of the first latch node is started, a sensing node of the second page buffer is pre-charged. The sensing node is connected to the second bit line. Data stored in the first latch is dumped into a second latch of the first page buffer during the pre-charging of the sensing node of the second page buffer.

公开(公告)号：US09349482B2

公开(公告)日：2016-05-24

申请号：US14639331

申请日：2015-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-Suk Kim ,  Il Han Park ,  Jung-Ho Song

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C16/107 ,  G11C16/26

Abstract: A method of programming a nonvolatile memory device is provided which includes applying a program voltage to selected ones of a plurality of memory cells; applying a selected one of a plurality of verification voltages after pre-charging bit lines connected to memory cells to which the program voltage is applied; sensing the memory cells to which the selected verification voltage is applied; selecting memory cells programmed to a target state referring to the sensing result and target state data; and determining whether programming of the selected memory cells is passed or failed.

Abstract translation: 提供了一种编程非易失性存储器件的方法，其包括将编程电压施加到多个存储器单元中的选定的存储器单元; 在连接到应用了编程电压的存储单元的位线预充电之后施加多个验证电压中的选定的一个; 感测所选择的验证电压被施加到的存储器单元; 参考感测结果和目标状态数据选择被编程到目标状态的存储器单元; 以及确定所选择的存储器单元的编程是否通过或失败。