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116 条记录 (耗时 0.043 秒)

    Semiconductor memory device with synchronous dram whose speed grade is not limited
    61.
    发明授权
    Semiconductor memory device with synchronous dram whose speed grade is not limited 失效
    具有同步电路的半导体存储器件，速度等级不受限制

    公开(公告)号：US5550784A

    公开(公告)日：1996-08-27

    申请号：US534270

    申请日：1995-09-26

    申请人： Yasuhiro Takai

    发明人： Yasuhiro Takai

    IPC分类号： G11C11/413 ,  G11C7/10 ,  G11C11/407 ,  G11C8/00

    CPC分类号： G11C7/1072 ,  G11C7/1039

    摘要： The semiconductor memory device disclosed includes a burst counter in a first stage of pipeline, a column switch latch portion in a second stage of the pipeline and an output data latch circuit in a third stage. In the operation mode with CAS latency of 2, as a control signal of the burst counter, a clock signal is outputted and, as a control signal of the column switch latch portion, a logical sum OR fixed to a high level by a mode signal is outputted. The device further includes a delay circuit and an output controller. The data output circuit is arranged such that it supplies, as a control signal of the output data latch circuit, a logical product AND of the inversion of the mode signal and the clock signal, and a logical sum OR of a signal delayed through the delay circuit and a logical product AND of the mode signal. In the synchronous DRAM thus configured, the speed grade in the operation mode with CAS latency of 2 is not restricted.

    摘要翻译： 所公开的半导体存储器件包括在流水线的第一级中的突发计数器，在流水线的第二级中的列开关锁存部分和第三级的输出数据锁存电路。 在CAS等待时间为2的运行模式中，作为脉冲串计数器的控制信号，输出时钟信号，作为列切换锁存部的控制信号，通过模式信号将逻辑和OR或固定为高电平 被输出。 该装置还包括延迟电路和输出控制器。 数据输出电路被布置成使得它作为输出数据锁存电路的控制信号提供模式信号与时钟信号的反相的逻辑积AND和通过延迟延迟的信号的逻辑和或 电路和模式信号的逻辑积AND。 在如此配置的同步DRAM中，CAS等待时间为2的运行模式的速度等级不受限制。

    Compact multi-functional image forming apparatus
    62.
    发明授权
    Compact multi-functional image forming apparatus 失效
    紧凑型多功能成像设备

    公开(公告)号：US5537199A

    公开(公告)日：1996-07-16

    申请号：US429428

    申请日：1995-05-01

    申请人： Yasuhiro Takai ,  Hirokazu Tanaka

    发明人： Yasuhiro Takai ,  Hirokazu Tanaka

    IPC分类号： G03G15/00 ,  G03G15/01 ,  G03G15/04 ,  G03G15/08 ,  G03G15/34 ,  G03G21/00

    CPC分类号： G03G15/0142 ,  G03G15/0163 ,  G03G15/344 ,  G03G2215/0497

    摘要： An image forming apparatus includes a photoreceptor formed by a transparent support member, a transparent conductive layer, an optical semiconductor layer, and an insulation layer stacked in this order, as well as developing units corresponding to black, yellow, magenta, and cyan provided at an outer periphery thereof. Exposure units corresponding to respective developing units are provided in the photoreceptor. Fixing units are arranged near respective developing devices at the outer periphery of the photoreceptor. Feeding units are provided for feeding a sheet A along the outer periphery of the photoreceptor from a paper feeding cassette to a first developing device and between the developing devices. Paper ejection units are provided corresponding to respective fixing units and sheet A is fed or ejected by switching the position of the fixing unit.

    摘要翻译： 图像形成装置包括由透明支撑构件，透明导电层，光学半导体层和依次堆叠的绝缘层形成的感光体，以及对应于黑色，黄色，品红色和青色的显影单元 其外围。 在感光体中设置与各显影单元对应的曝光单元。 定影单元布置在感光体的外周附近的各显影装置附近。 供给单元被设置用于沿着感光体的外周将纸张A从供纸盒馈送到第一显影装置并且在显影装置之间。 纸张排出单元对应于相应的固定单元设置，并且通过切换定影单元的位置来输送或排出纸张A.

    Semiconductor memory device synchronous with external clock signal for outputting data bits through a small number of data lines
    63.
    发明授权
    Semiconductor memory device synchronous with external clock signal for outputting data bits through a small number of data lines 失效
    半导体存储器件与外部时钟信号同步，用于通过少量数据线输出数据位

    公开(公告)号：US5426606A

    公开(公告)日：1995-06-20

    申请号：US221574

    申请日：1994-04-01

    申请人： Yasuhiro Takai

    发明人： Yasuhiro Takai

    IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C11/407 ,  G11C11/4096 ,  G11C8/00

    CPC分类号： G11C11/4096 ,  G11C7/1039 ,  G11C7/1072

    摘要： A synchronous dynamic random access memory device allows an external device to sequentially access read-out data bits in synchronous with a system clock signal, and a column addressing system incorporated in the synchronous dynamic random access memory device forms a plurlaity of pipeline stages together with an input/output unit for sequentially supplying data bits to a data port in response to a column address internally incremented in synchronism with the system clock signal, thereby propagating the data bits through a single data bus.

    摘要翻译： 同步动态随机存取存储器件允许外部设备与系统时钟信号同步地顺序地访问读出数据位，并且并入在同步动态随机存取存储器件中的列寻址系统与流水线级一起形成多个 输入/输出单元，用于响应于与系统时钟信号同步地内部递增的列地址来顺序地向数据端口提供数据位，从而通过单个数据总线传播数据位。

    Timing control circuit and semiconductor storage device
    66.
    发明授权
    Timing control circuit and semiconductor storage device 有权
    定时控制电路和半导体存储设备

    公开(公告)号：US07973582B2

    公开(公告)日：2011-07-05

    申请号：US12205668

    申请日：2008-09-05

    申请人： Akira Ide ,  Yasuhiro Takai ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Hiroaki Nakaya

    发明人： Akira Ide ,  Yasuhiro Takai ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Hiroaki Nakaya

    IPC分类号： H03H11/26

    CPC分类号： H03K5/15033

    摘要： Disclosed is a timing control circuit which receives a first clock having a period T1 and a group of second clocks of L different phases (where L is a positive integer) spaced apart from each other at substantially equal intervals and which generates a fine timing signal delayed from the rising edge of the first clock by a delay td of approximately td=m·T1+n·(T2/L), where m and n are non-negative integers. The timing control circuit has a coarse delay circuit and a fine delay circuit. The coarse delay circuit counts the rising edges of the first clock after an activate signal is activated and generates a coarse timing signal delayed from the first clock by approximately m·T1. The fine delay circuit has a circuit which, after the activate signal is activated, detects a second clock, which has a rising edge that immediately follows the rising edge of the first clock, from among the group of L-phase second clocks. Using the edge-detection information, the fine delay circuit generates a fine timing signal for which the amount of delay from the coarse timing signal is approximately n·(T2/L). The values of m and n can be set by registers.

    摘要翻译： 公开了一种定时控制电路，其以基本相等的间隔接收具有周期T1和L个不同相位（其中L是正整数）的第二时钟的一组第一时钟，并且产生延迟的精细定时信号 从第一时钟的上升沿开始约td = m·T1 + n·（T2 / L）的延迟td，其中m和n是非负整数。 定时控制电路具有粗略延迟电路和精细延迟电路。 粗略延迟电路在激活信号激活后对第一时钟的上升沿进行计数，并产生从第一个时钟延迟大约m·T1的粗略定时信号。 精细延迟电路具有在激活信号被激活之后，从一组L相第二时钟中检测出具有紧跟第一时钟的上升沿的上升沿的第二时钟的电路。 利用边缘检测信息，精细延迟电路产生从粗定时信号的延迟量近似为n·（T2 / L）的精细定时信号。 m和n的值可以由寄存器设置。

    Semiconductor device
    68.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07903492B2

    公开(公告)日：2011-03-08

    申请号：US12314860

    申请日：2008-12-17

    申请人： Akira Ide ,  Yasuhiro Takai ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Hiroaki Nakaya

    发明人： Akira Ide ,  Yasuhiro Takai ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Hiroaki Nakaya

    IPC分类号： G11C7/00

    CPC分类号： G11C7/22 ,  G11C7/04 ,  G11C7/1048 ,  G11C7/12 ,  G11C7/20 ,  G11C7/222 ,  G11C11/4094 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10897 ,  H03K5/15066

    摘要： Disclosed is a semiconductor device including a first clock generator that generates a first clock signal having a first period from an input clock signal, a second clock generator that generates a second clock signal having a second period from the input clock signal, and a timing generator that receives the first clock signal, the second clock signal, an activation signal from a command decoder and a selection signal for selecting the delay time from a timing register to produce a timing signal delayed as from activation of the activation signal by a delay equal to a sum of a time equal to a preset number m prescribed by the selection signal times the first period and a time equal to another preset number n prescribed by the selection signal times the second period. The timing register holds the values of m and n. These values are set in the timing register in an initialization sequence at the time of a mode register set command. In the operating states, the timing signals are output from the timing generator at a desired timing based on the information stored in the timing register (FIG. 6).

    摘要翻译： 公开了一种半导体器件，包括第一时钟发生器，其从输入时钟信号产生具有第一周期的第一时钟信号;第二时钟发生器，其从输入时钟信号产生具有第二周期的第二时钟信号;以及定时发生器 其接收第一时钟信号，第二时钟信号，来自命令解码器的激活信号和用于从定时寄存器选择延迟时间的选择信号，以产生从激活信号的激活延迟等于 等于由选择信号规定的预定数量m的时间等于第一周期的时间和等于由选择信号规定的另一个预设数量n的时间乘以第二周期的时间之和。 定时寄存器保存m和n的值。 这些值在模式寄存器设置命令时以初始化顺序设置在定时寄存器中。 在操作状态下，基于定时寄存器（图6）中存储的信息，定时信号以定时发生器输出。

    Duty detection circuit, DLL circuit using the same, semiconductor memory circuit, and data processing system
    69.
    发明授权
    Duty detection circuit, DLL circuit using the same, semiconductor memory circuit, and data processing system 有权
    占空比检测电路，使用相同的DLL电路，半导体存储器电路和数据处理系统

    公开(公告)号：US07719921B2

    公开(公告)日：2010-05-18

    申请号：US12170730

    申请日：2008-07-10

    申请人： Koji Kuroki ,  Yasuhiro Takai

    发明人： Koji Kuroki ,  Yasuhiro Takai

    IPC分类号： G11C11/00

    CPC分类号： G11C11/4076 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0814 ,  H03L7/087

    摘要： A duty detection circuit includes discharge transistors, charge transistors, detection lines, and a comparator circuit that detects a potential difference of these detection lines, and also includes a gate circuit that controls the discharge transistors and the charge transistors in response to the internal clock signal of an even cycle. As a result, the detection lines are charged and discharged in response to the internal clock signal of the even cycle. Consequently, the duty detection circuit can be applied to a multi-phase DLL circuit, and a potential difference appearing in the detection line can be sufficiently secured.

    摘要翻译： 占空比检测电路包括放电晶体管，充电晶体管，检测线和检测这些检测线的电位差的比较器电路，还包括根据内部时钟信号控制放电晶体管和充电晶体管的门电路 的偶数周期。 结果，响应于偶数周期的内部时钟信号，检测线被充电和放电。 因此，占空比检测电路可以应用于多相DLL电路，并且可以充分确保出现在检测线中的电位差。