公开(公告)号：US08114755B2

公开(公告)日：2012-02-14

申请号：US12146143

申请日：2008-06-25

申请人： Ichiro Mizushima ,  Yoshio Ozawa ,  Takashi Nakao ,  Akihito Yamamoto ,  Takashi Suzuki ,  Masahiro Kiyotoshi ,  Minako Inukai ,  Kaori Umezawa ,  Hiroaki Yamada

发明人： Ichiro Mizushima ,  Yoshio Ozawa ,  Takashi Nakao ,  Akihito Yamamoto ,  Takashi Suzuki ,  Masahiro Kiyotoshi ,  Minako Inukai ,  Kaori Umezawa ,  Hiroaki Yamada

IPC分类号： H01L21/76

CPC分类号： H01L21/764

摘要： A method of manufacturing a semiconductor device includes removing a part of a semiconductor substrate to form a protruding portion and a recess portion in a surface area of the semiconductor substrate, forming a first epitaxial semiconductor layer in the recess portion, forming a second epitaxial semiconductor layer on the protruding portion and the first epitaxial semiconductor layer, removing a first part of the second epitaxial semiconductor layer with a second part of the second epitaxial semiconductor layer left to expose a part of the first epitaxial semiconductor layer, and etching the first epitaxial semiconductor layer from the exposed part of the first epitaxial semiconductor layer to form a cavity under the second part of the second epitaxial semiconductor layer.

摘要翻译： 一种制造半导体器件的方法包括：去除半导体衬底的一部分以在半导体衬底的表面区域中形成突出部分和凹陷部分，在凹部中形成第一外延半导体层，形成第二外延半导体层 在所述突出部分和所述第一外延半导体层上，用所述第二外延半导体层的第二部分去除所述第二外延半导体层的第一部分，以露出所述第一外延半导体层的一部分，并且蚀刻所述第一外延半导体层 从第一外延半导体层的暴露部分形成在第二外延半导体层的第二部分下面的空腔。

公开(公告)号：US07896970B2

公开(公告)日：2011-03-01

申请号：US11893752

申请日：2007-08-16

申请人： Hiroshi Tomita ,  Yuji Yamada ,  Hiroaki Yamada ,  Norio Ishikawa ,  Yumiko Abe

发明人： Hiroshi Tomita ,  Yuji Yamada ,  Hiroaki Yamada ,  Norio Ishikawa ,  Yumiko Abe

IPC分类号： H01L21/02

CPC分类号： H01L21/02052 ,  C11D7/08 ,  C11D7/34 ,  C11D7/36 ,  C11D11/0047

摘要： A semiconductor substrate cleaning liquid composition is provided that includes one or more types selected from the group consisting of a compound having at least two sulfonic acid groups per molecule, phytic acid, and a condensed phosphoric acid compound; an inorganic acid; and water. There is also provided a process for cleaning a semiconductor substrate that includes a first step of cleaning the semiconductor substrate using the semiconductor substrate cleaning liquid composition and, subsequent to the first step, a second step of cleaning the semiconductor substrate with pure water, ozone water formed by dissolving ozone gas in pure water, or aqueous hydrogen peroxide.

摘要翻译： 提供一种半导体衬底清洗液组合物，其包含一种或多种选自每分子具有至少两个磺酸基的化合物，植酸和缩合磷酸化合物的类型; 无机酸; 和水。 还提供了一种清洗半导体衬底的方法，该方法包括使用半导体衬底清洗液组合物清洗半导体衬底的第一步骤，在第一步骤之后，用纯水，臭氧水清洗半导体衬底的第二步骤 通过将臭氧气体溶解在纯水或过氧化氢水溶液中形成。

公开(公告)号：US07609714B2

公开(公告)日：2009-10-27

申请号：US10943490

申请日：2004-09-17

申请人： Hiroaki Yamada ,  Hideo Okeda ,  Kenichiro Tomita ,  Makoto Ishikawa

发明人： Hiroaki Yamada ,  Hideo Okeda ,  Kenichiro Tomita ,  Makoto Ishikawa

IPC分类号： H04L12/66

CPC分类号： H04L12/46 ,  G05B2219/14124 ,  H04L2012/5627

摘要： A duplexed network system is formed with a plurality of programmable controllers and two different networks. Each of the programmable controllers includes a CPU unit, a primary communication unit connected to one of these networks (the first network) and a secondary communication unit connected to the other of the networks (the second network). The primary communication unit serves to compile participation status of nodes connected to the first network. The CPU unit gives priority to the primary communication unit when a request to transmit a communication command is issued to both the primary and secondary communication units. The primary communication unit serves to judge, when a request to transmit a communication command to an addressee node is received from the CPU unit, whether transmission to the addressee node is possible based on the participation status of the first network, to transmit the communication command if the transmission is judged to be possible and to request the secondary communication unit to transmit the communication command if the transmission is judged to be not possible.

摘要翻译： 双工网络系统形成有多个可编程控制器和两个不同的网络。 每个可编程控制器包括CPU单元，连接到这些网络之一（第一网络）的主要通信单元和连接到另一个网络（第二网络）的次要通信单元。 主要通信单元用于编译连接到第一网络的节点的参与状态。 当发送通信命令的请求被发送给主要和次要通信单元时，CPU单元优先考虑主要通信单元。 主要通信单元用于判断从CPU单元接收到向收件人节点发送通信命令的请求时，基于第一网络的参与状态，是否可以发送到收件人节点，发送通信命令 如果传输被判定为可能，并且如果判断传输是不可能的，则请求副通信单元发送通信命令。

公开(公告)号：US20080308132A1

公开(公告)日：2008-12-18

申请号：US12129074

申请日：2008-05-29

申请人： Hiroshi Tomita ,  Hiroyasu Iimori ,  Hiroaki Yamada ,  Minako Inukai

发明人： Hiroshi Tomita ,  Hiroyasu Iimori ,  Hiroaki Yamada ,  Minako Inukai

IPC分类号： B08B3/12 ,  B08B3/08

CPC分类号： H01L21/02057 ,  B08B3/10 ,  B08B3/12 ,  C11D3/0052 ,  C11D11/0047 ,  H01L21/02052 ,  H01L21/67057

摘要： A method has been disclosed which cleans a semiconductor substrate using a cleaning liquid produced by mixing bubbles of a gas into an acid solution in which the gas has been dissolved to the saturated concentration and which brings the zeta potentials of the semiconductor substrate and adsorbed particles into the negative region by the introduction of an interfacial active agent. Alternatively, a semiconductor substrate is cleaned using a cleaning liquid produced by mixing bubbles of a gas into an alkaline solution in which the gas has been dissolved to the saturated concentration and whose pH is 9 or more.

摘要翻译： 已经公开了一种方法，其使用通过将气体的气泡混合到其中已经溶解气体的酸溶液达到饱和浓度并且将半导体衬底和吸附的颗粒的ζ电位引入的清洗液清洗半导体衬底 通过引入界面活性剂的负面区域。 或者，使用将气体的气泡混合到其中溶解有气体至饱和浓度并且pH为9以上的碱性溶液中制备的清洗液来清洗半导体衬底。

公开(公告)号：US20060081335A1

公开(公告)日：2006-04-20

申请号：US11246140

申请日：2005-10-11

申请人： Hiroyasu Iimori ,  Hiroshi Tomita ,  Hiroaki Yamada

发明人： Hiroyasu Iimori ,  Hiroshi Tomita ,  Hiroaki Yamada

IPC分类号： C23F1/00 ,  C03C15/00

CPC分类号： H01L21/67253 ,  H01L21/67086

摘要： According to the present invention, there is provided a semiconductor substrate processing apparatus comprising: a processing bath which etches a semiconductor substrate by dipping the semiconductor substrate into a processing solution; an outer bath which is positioned outside said processing bath and receives the processing solution overflowing from said processing bath; a circulation channel which resupplies the processing solution discharged from said outer bath to said processing bath; a heater which adjusts a temperature of the processing solution flowing through said circulation channel; a filter which removes foreign matter in the processing solution flowing through said circulation channel; and a controller which measures, after the semiconductor substrate is loaded into said processing bath, one of the temperature of the processing solution in said processing bath and a time during which the temperature of the processing solution restores a predetermined temperature, calculates a processing time during which the semiconductor substrate is etched on the basis of the measurement result, and etches the semiconductor substrate on the basis of the calculated processing time.

摘要翻译： 根据本发明，提供了一种半导体衬底处理装置，包括：通过将半导体衬底浸入处理溶液来蚀刻半导体衬底的处理槽; 位于所述处理槽外部并接收从所述处理槽溢出的处理溶液的外浴; 循环通道，其将从所述外浴排出的处理溶液补给所述处理槽; 调节流过所述循环通道的处理溶液的温度的加热器; 过滤器，其去除流过所述循环通道的处理溶液中的异物; 以及控制器，其在半导体衬底被加载到所述处理槽中之后，测量所述处理槽中的处理溶液的温度和处理溶液的温度恢复预定温度的时间之一，计算处理溶液的处理时间 基于测量结果蚀刻半导体衬底，并且基于所计算的处理时间蚀刻半导体衬底。

公开(公告)号：US06947653B2

公开(公告)日：2005-09-20

申请号：US09977065

申请日：2001-10-12

申请人： Jyoti Kiron Bhardwaj ,  Robert James Brainard ,  Zi-Wen Dong ,  David Dougherty ,  Erik W. Egan ,  Niranjan Gopinathan ,  David K. Nakamoto ,  Thomas Thuan Nguyen ,  Sanjay M. Thekdi ,  Anantharaman Vaidyanathan ,  Hiroaki Yamada ,  Yingchao Yan

发明人： Jyoti Kiron Bhardwaj ,  Robert James Brainard ,  Zi-Wen Dong ,  David Dougherty ,  Erik W. Egan ,  Niranjan Gopinathan ,  David K. Nakamoto ,  Thomas Thuan Nguyen ,  Sanjay M. Thekdi ,  Anantharaman Vaidyanathan ,  Hiroaki Yamada ,  Yingchao Yan

IPC分类号： G02B6/12 ,  G02B6/13 ,  G02B6/136 ,  G02B6/34 ,  G02B6/10 ,  G02F1/295

CPC分类号： G02B6/1203 ,  G02B6/13 ,  G02B6/136 ,  G02B2006/12097 ,  G02B2006/12176

摘要： A planar lightwave circuit includes at least one optical waveguide core, and at least one feature proximate the core having a stress-engineered property to balance stress and therefore minimize birefringence affecting the core. A protective passivation layer is formed over the core and the feature to be substantially non-interfering with the balanced stress provided by the feature. The stress balancing feature may be an overcladding layer formed over the core, doped to have a coefficient of thermal expansion approximately matched to that of an underlying substrate, to symmetrically distribute stress in an undercladding between the overcladding and the substrate, away from the core. The protective passivation layer is formed to have a coefficient of thermal expansion approximately matched to that of the overcladding. In one exemplary embodiment, the passivation layer is formed from silicon nitride. Related concepts of stress release grooves, and core overetching, are also disclosed.

摘要翻译： 平面光波电路包括至少一个光波导芯，并且靠近芯的至少一个特征具有应力工程化特性以平衡应力，从而最小化影响芯的双折射。 在芯上形成保护性钝化层，并且该特征基本上不受由特征提供的平衡应力的干扰。 应力平衡特征可以是在芯上形成的外包层，被掺杂以具有与下层衬底的热膨胀系数近似匹配的热膨胀系数，以便在外包层和衬底之间的下包层对称地分布应力。 保护钝化层形成为具有与外包层大致匹配的热膨胀系数。 在一个示例性实施例中，钝化层由氮化硅形成。 还公开了应力释放槽和芯过蚀刻的相关概念。

公开(公告)号：US06759938B2

公开(公告)日：2004-07-06

申请号：US10131079

申请日：2002-04-25

申请人： Norio Matsumura ,  Haruhito Ohtsuka ,  Hiroaki Yamada ,  Tsuyoshi Nakamura

发明人： Norio Matsumura ,  Haruhito Ohtsuka ,  Hiroaki Yamada ,  Tsuyoshi Nakamura

IPC分类号： H01H8512

CPC分类号： H01H85/044 ,  H01H2085/0555

摘要： A fuse circuit (11) having a plurality of terminals (22, 23) provided on a common joint plate (21) and a fuse circuit (11′) having a plurality of terminals (22′, 23′) provided on a common joint plate (21′) are incorporated into a housing (12), thereby constituting a fuse link assembly (10). The plurality of fuse circuits (11, 11′) are provided with circuit connection portions (27, 27′) which share a power input portion. The fuse circuits (11, 11′) are incorporated into the housing (12) in parallel. As a result, the number of circuits is increased, by means of only enlargement of widthwise direction Y which is easy to increase while enlargement of longitudinal direction X stemming from packaging of circuits is minimized.

摘要翻译： 一种具有设置在公共接头板（21）上的多个端子（22,23）和熔断器电路（11'）的保险丝电路（11），其具有设置在公共接头上的多个端子（22'，23'） 板（21'）结合到壳体（12）中，从而构成熔断体组件（10）。 多个保险丝电路（11,11'）设有共用电力输入部分的电路连接部分（27,27'）。 保险丝电路（11,11'）并入并入壳体（12）中。 结果，通过仅扩大容易增大的宽度方向Y，同时由于电路封装引起的纵向方向X的放大最小化，电路的数量增加。

公开(公告)号：US06697553B2

公开(公告)日：2004-02-24

申请号：US10077581

申请日：2002-02-15

申请人： Jyoti Kiron Bhardwaj ,  Robert James Brainard ,  David J. Chapman ,  Douglas E. Crafts ,  Zi-Wen Dong ,  David Dougherty ,  Erik W. Egan ,  James F. Farrell ,  Mark B. Farrelly ,  Niranjan Gopinathan ,  Kenzo Ishida ,  David K. Nakamoto ,  Thomas Thuan Nguyen ,  Suresh Ramalingam ,  Steven M. Swain ,  Sanjay M. Thekdi ,  Anantharaman Vaidyanathan ,  Hiroaki Yamada ,  Yingchao Yan

发明人： Jyoti Kiron Bhardwaj ,  Robert James Brainard ,  David J. Chapman ,  Douglas E. Crafts ,  Zi-Wen Dong ,  David Dougherty ,  Erik W. Egan ,  James F. Farrell ,  Mark B. Farrelly ,  Niranjan Gopinathan ,  Kenzo Ishida ,  David K. Nakamoto ,  Thomas Thuan Nguyen ,  Suresh Ramalingam ,  Steven M. Swain ,  Sanjay M. Thekdi ,  Anantharaman Vaidyanathan ,  Hiroaki Yamada ,  Yingchao Yan

IPC分类号： G02B634

CPC分类号： G02B6/12011 ,  G02B6/105 ,  G02B6/12 ,  G02B6/12016 ,  G02B6/12021 ,  G02B6/12026

摘要： A planar lightwave circuit includes an arrayed waveguide grating (AWG), with input and output waveguides, partially curved array waveguides with respective length differences, and planar waveguide regions for focusing optical energy between the input/output and array waveguides. Optimal waveguide widths and spacing along the planar waveguide region facets are disclosed, which are largely determinative of AWG size and optical performance. Also disclosed are optimal cross-sectional waveguide dimensions (e.g., width and height); modified index of refraction difference between the waveguide core and cladding regions; and optimal array waveguide lengths, path length differences, and free spectral range. These features, especially when combined with advanced fiber attachment, passivation and packaging techniques, result in high-yield, high-performance AWGs (both gaussian and flattop versions).

摘要翻译： 平面光波电路包括阵列波导光栅（AWG），其具有输入和输出波导，具有相应长度差的部分弯曲阵列波导和用于在输入/输出和阵列波导之间聚焦光能的平面波导区域。 公开了沿着平面波导区域面的最佳波导宽度和间距，其主要决定于AWG尺寸和光学性能。 还公开了最佳横截面波导尺寸（例如，宽度和高度）; 波导芯和包层区之间的折射率差异; 和最佳阵列波导长度，路径长度差和自由光谱范围。 这些特性，特别是结合先进的光纤附着，钝化和封装技术，可以获得高产出，高性能的AWG（高斯型和平板型）。

公开(公告)号：US06589060B2

公开(公告)日：2003-07-08

申请号：US10067327

申请日：2002-02-07

申请人： Hiroaki Yamada

发明人： Hiroaki Yamada

IPC分类号： H01R1200

CPC分类号： H01R43/18 ,  H01R9/223 ,  H01R13/516 ,  H01R2201/26

摘要： In an electric connection box-producing method, block members (2) for connecting electrical circuit parts are provided on a mounting frame (4), and this method includes a block member-molding step of molding individual block members (2) separate from one another, a block member-combining step of arranging the plurality of block members (2) in the irrespective predetermined positions, and welding these block members together to form a block assembly (3), and a block assembly-mounting step of fixedly securing the block assembly (3) to the mounting frame (4).

公开(公告)号：US06522997B1

公开(公告)日：2003-02-18

申请号：US08953998

申请日：1997-10-20

申请人： Hiroaki Yamada

发明人： Hiroaki Yamada

IPC分类号： G06G748

CPC分类号： G06F17/5018 ,  G06F2217/10

摘要： The method includes the steps of: calculating a direction-dependent distribution of ejected particles from a target, dividing a range of the vertical angle &thgr;, with respect to a direction perpendicular to the surface of the target, into sections of an equal interval, counting a number of the ejected particles for every section of the vertical angle &thgr;, and calculating a vertical distribution function by interpolating the counted numbers of the ejected particles as a function of the vertical angle &thgr;. The method also includes determining values of the vertical angle &thgr; likely to emerge in a random process of a particle ejection from the target using the vertical distribution function based on a rejection method, determining values of the horizontal angle &phgr;, measured from a direction in the surface plane of the target, likely to emerge in a random process of a particle ejection from the target, and calculating tracks of sputtered particles in a sputtering arrangement using the values of the vertical angles and the horizontal angles determined by the third step and the fourth step in accordance with the Monte Carlo method.

摘要翻译： 该方法包括以下步骤：计算来自目标的喷射粒子的方向相关分布，将相对于目标表面垂直的方向的垂直角度θ的范围分成等间隔的部分，计数 用于垂直角度θ的每个部分的多个喷出的颗粒，并且通过内插所排出的颗粒的计数的数量作为垂直角度θ的函数来计算垂直分布函数。 该方法还包括使用基于拒绝方法的垂直分布函数来确定可能从粒子喷出的粒子的随机过程中可能出现的垂直角θ的值，确定从水平角度phi中的方向测量的水平角度phi的值 目标的表面平面可能以从粒子射出目标的随机过程出现，并且使用由第三步骤确定的垂直角度和水平角度的值来计算溅射装置中的溅射粒子的轨迹 按照蒙特卡罗方法进行。