公开(公告)号：US07724990B2

公开(公告)日：2010-05-25

申请号：US12171488

申请日：2008-07-11

Applicant: Kenzo Ishida

Inventor： Kenzo Ishida

IPC: G02B6/12 ,  G02B6/26 ,  G02B6/30

CPC classification number: G02B6/2852 ,  G02B6/12019 ,  H04B10/0795 ,  H04B10/25

Abstract: A technique for monitoring optical power in a fiber array unit having a plurality of optical transmission waveguides terminating at an edge thereof for carrying optical signals to and/or from a PLC. A tapping filter is placed within a slit formed in the substrate and interrupting the transmission channels, thereby tapping at least some of the optical power from the channels and directing the tapped optical power toward respective photodetector channels for detection, while allowing other optical power to continue transmission in the at least one channel of the fiber array unit.

Abstract translation: 一种用于监测光纤阵列单元中的光功率的技术，其具有终止于其边缘处的多个光传输波导，用于向PLC和/或从PLC携载光信号。 分接滤波器被放置在形成在衬底中的狭缝中并且中断传输通道，从而从通道中抽出至少一些光功率，并将分接的光功率引导到相应的光电检测器通道用于检测，同时允许其他光功率继续 在光纤阵列单元的至少一个通道中的传输。

公开(公告)号：US06422303B1

公开(公告)日：2002-07-23

申请号：US09524798

申请日：2000-03-14

Applicant: Kenzo Ishida ,  Shinya Endo ,  Daryl J. Nelson

Inventor： Kenzo Ishida ,  Shinya Endo ,  Daryl J. Nelson

IPC: F28F700

CPC classification number: G06F1/20 ,  G10K11/178

Abstract: A heat dissipation device comprising a thermally conductive, hollow housing having a fan and an active anti-noise module disposed within the hollow housing. The hollow housing may include a plurality of fins disposed therein to increase the surface area for convective heat transfer. The heat dissipation device further may further include heat pipes for the transportation and dispersion of heat to and about an external surface of the hollow housing.

Abstract translation: 一种散热装置，包括导热的中空壳体，其具有设置在中空壳体内的风扇和主动抗噪声模块。 中空壳体可以包括设置在其中的多个翅片，以增加用于对流热传递的表面积。 散热装置还可以进一步包括用于将热量输送和分散到中空壳体的外表面的周围的热管。

公开(公告)号：US06020561A

公开(公告)日：2000-02-01

申请号：US745470

申请日：1996-11-12

Applicant: Kenzo Ishida ,  Yohko Mashimoto ,  Kinya Ichikawa

Inventor： Kenzo Ishida ,  Yohko Mashimoto ,  Kinya Ichikawa

IPC: H01L21/48 ,  H01L21/60 ,  H01L23/498 ,  H05K1/11 ,  H05K3/12 ,  H05K3/34 ,  H01R9/09

CPC classification number: H01L24/81 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49894 ,  H01L24/14 ,  H05K3/3484 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/1403 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H05K1/114 ,  H05K2201/09472 ,  H05K2201/10674 ,  H05K2203/043 ,  H05K3/1216

Abstract: A printed circuit substrate having solder bumps formed on pad-on-via contacts and pad-off-via contacts. The printed circuit substrate has at least one pad-on-via contact and at least one pad-off-via contact. A first solder bump is on the pad-on-via contact and a second solder bump is on the pad-off-via contact. The first and second solder bumps are substantially the same height as measured above a horizontal plane that is substantially co-planar to the pad-off-via contact.

Abstract translation: 一种印刷电路基板，其具有形成在通孔触点和通过通孔触点上的焊料凸块。 印刷电路基板具有至少一个焊盘通孔接触件和至少一个焊盘通过接触件。 第一焊料凸块位于通孔焊盘上，第二焊料凸块位于焊盘通过接触点上。 第一和第二焊料凸块基本上与在与焊接通孔接触件基本上共面的水平面上测量的高度相同。

公开(公告)号：US5660321A

公开(公告)日：1997-08-26

申请号：US623676

申请日：1996-03-29

Applicant: Kenzo Ishida ,  Yohko Mashimoto ,  Kinya Ichikawa

Inventor： Kenzo Ishida ,  Yohko Mashimoto ,  Kinya Ichikawa

IPC: H01L21/48 ,  H01L21/60 ,  H01L23/498 ,  H05K1/11 ,  H05K3/12 ,  H05K3/34

CPC classification number: H01L24/81 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49894 ,  H01L24/14 ,  H05K3/3484 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/1403 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H05K1/114 ,  H05K2201/09472 ,  H05K2201/10674 ,  H05K2203/043 ,  H05K3/1216

Abstract: An method for depositing solder onto the pad-on and pad-off via contacts of a substrate is disclosed. In one embodiment the present invention includes positioning a mask having a first opening of a first diameter and a second opening of a second diameter over a substrate having both pad-on and pad-off via contacts. The substrate is positioned over the substrate such that the first opening is positioned over the pad-on via contact and the second opening is positioned over the pad-off via contact. Solder of a first volume and solder of a second volume are deposited onto the pad-on and pad-off via contacts, respectively, by forcing a solder paste through the mask openings. In this manner, solder bumps having a uniform height and volume above the pad-on via contact plane is established after reflowing the deposited solder.

Abstract translation: 公开了一种通过衬底的触点将焊料沉积到焊盘上和焊盘上的方法。 在一个实施例中，本发明包括将具有第一直径的第一开口和第二直径的第二开口的掩模定位在具有经由接触件的衬垫和衬垫的衬底上。 衬底被定位在衬底上，使得第一开口定位在衬垫穿过接触件上方，并且第二开口通过触点定位在焊盘上方。 第一体积的焊料和第二体积的焊料通过分别通过迫使焊膏通过掩模开口的触点而沉积到焊盘和焊盘上。 以这种方式，在回流沉积的焊料之后建立具有均匀的高度和体积高于焊盘通孔接触面的焊料凸块。

公开(公告)号：US20070196050A1

公开(公告)日：2007-08-23

申请号：US11675896

申请日：2007-02-16

Applicant: Kenzo ISHIDA ,  Alan TAFAPOLSKY ,  Takaharu FUJIYAMA

Inventor： Kenzo ISHIDA ,  Alan TAFAPOLSKY ,  Takaharu FUJIYAMA

IPC: G02B6/26

CPC classification number: G02B6/125 ,  G02B6/1228

Abstract: A funnel-type planar lightwave circuit (PLC) optical splitter having an input optical waveguide, a slab waveguide receiving the input optical signal from the input optical waveguide, and output waveguides projecting from the slab region. The region connecting the slab waveguide to the output waveguides is characterized by a segmented taper structure. In another additional, or alternative aspect of the present invention, a cladding mode absorption region runs along either or both sides of the input optical waveguide. A funnel-type splitter with both a cladding mode absorption region and a segmented taper structure provides a “super” low loss splitter design, when considering both insertion loss and polarization dependent loss. Advantageously, the disclosed funnel-type PLC splitter does not require a quartz substrate due to its very low PDL, and a silicon substrate can be used. Silicon substrates are known to be lower cost, with a higher resistance to fracture.

Abstract translation: 具有输入光波导的漏斗型平面光波回路（PLC）光分路器，接收来自输入光波导的输入光信号的平板波导和从板区域突出的输出波导。 将平板波导连接到输出波导的区域的特征在于分段锥形结构。 在本发明的另一个或另一方面中，包层模式吸收区沿输入光波导的一侧或两侧延伸。 当考虑插入损耗和偏振相关损耗时，具有包层模式吸收区域和分段锥形结构的漏斗型分流器提供了“超级”低损耗分离器设计。 有利地，所公开的漏斗型PLC分离器由于其非常低的PDL而不需要石英基板，并且可以使用硅基板。 已知硅基板具有较低的成本，具有较高的抗断裂性。

公开(公告)号：US06173576B1

公开(公告)日：2001-01-16

申请号：US09276254

申请日：1999-03-25

Applicant: Kenzo Ishida ,  Shuji Inoue

Inventor： Kenzo Ishida ,  Shuji Inoue

IPC: F25B2102

CPC classification number: F25B21/02 ,  F28D15/02 ,  H01L23/38 ,  H01L23/467 ,  H01L35/30 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A cooling unit for an integrated circuit. The cooling unit may include a peltier device that may be coupled to the integrated circuit and a plurality of fins that are thermally coupled to the peltier device. The fins may be separated by at least one channel. The cooling unit may include a fan that generates a flow of fluid through the channel.

Abstract translation: 集成电路的冷却单元。 冷却单元可以包括可以耦合到集成电路的皮肤器装置和热耦合到珀耳帖装置的多个鳍片。 翅片可以通过至少一个通道分开。 冷却单元可以包括产生通过通道的流体流的风扇。

公开(公告)号：US20090016716A1

公开(公告)日：2009-01-15

申请号：US12171488

申请日：2008-07-11

Applicant: Kenzo ISHIDA

Inventor： Kenzo ISHIDA

IPC: G02B6/12 ,  H04B10/08

CPC classification number: G02B6/2852 ,  G02B6/12019 ,  H04B10/0795 ,  H04B10/25

Abstract: A technique for monitoring optical power in a fiber array unit having a plurality of optical transmission waveguides terminating at an edge thereof for carrying optical signals to and/or from a PLC. A tapping filter is placed within a slit formed in the substrate and interrupting the transmission channels, thereby tapping at least some of the optical power from the channels and directing the tapped optical power toward respective photodetector channels for detection, while allowing other optical power to continue transmission in the at least one channel of the fiber array unit.

Abstract translation: 一种用于监测光纤阵列单元中的光功率的技术，其具有终止于其边缘处的多个光传输波导，用于向PLC和/或从PLC携载光信号。 分接滤波器被放置在形成在衬底中的狭缝中并且中断传输通道，从而从通道中抽出至少一些光功率，并将分接的光功率引导到相应的光电检测器通道用于检测，同时允许其他光功率继续 在光纤阵列单元的至少一个通道中的传输。

公开(公告)号：US06798137B2

公开(公告)日：2004-09-28

申请号：US10302282

申请日：2002-11-22

Applicant: Kenzo Ishida

Inventor： Kenzo Ishida

IPC: H01J162

CPC classification number: H01L27/3276 ,  H01L27/3288 ,  H01L51/524 ,  H01L51/56 ,  H05B33/10 ,  H05B33/26 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49149

Abstract: An apparatus and method for warpage compensation of a display panel substrate assembly are described. A method and apparatus for warpage compensation of a display panel substrate assembly are described. In one embodiment, the method includes the selection of a substrate having a substrate warpage level exceeding a warpage tolerance level. Once selected, a plurality of conductive bumps are formed over an area of the selected substrate. Once formed, a thermal process is applied to the plurality of conductive bumps to obtain a virtual plane over the area of the selected substrate have a coplanarity level below a coplanarity specification level. As such, utilizing embodiments of the present invention, lower cost substrates with substandard warpage levels may be utilized to form OLED panel substrate assemblies when compensated utilizing embodiments of the present invention.

公开(公告)号：US06697553B2

公开(公告)日：2004-02-24

申请号：US10077581

申请日：2002-02-15

Applicant: Jyoti Kiron Bhardwaj ,  Robert James Brainard ,  David J. Chapman ,  Douglas E. Crafts ,  Zi-Wen Dong ,  David Dougherty ,  Erik W. Egan ,  James F. Farrell ,  Mark B. Farrelly ,  Niranjan Gopinathan ,  Kenzo Ishida ,  David K. Nakamoto ,  Thomas Thuan Nguyen ,  Suresh Ramalingam ,  Steven M. Swain ,  Sanjay M. Thekdi ,  Anantharaman Vaidyanathan ,  Hiroaki Yamada ,  Yingchao Yan

Inventor： Jyoti Kiron Bhardwaj ,  Robert James Brainard ,  David J. Chapman ,  Douglas E. Crafts ,  Zi-Wen Dong ,  David Dougherty ,  Erik W. Egan ,  James F. Farrell ,  Mark B. Farrelly ,  Niranjan Gopinathan ,  Kenzo Ishida ,  David K. Nakamoto ,  Thomas Thuan Nguyen ,  Suresh Ramalingam ,  Steven M. Swain ,  Sanjay M. Thekdi ,  Anantharaman Vaidyanathan ,  Hiroaki Yamada ,  Yingchao Yan

IPC: G02B634

CPC classification number: G02B6/12011 ,  G02B6/105 ,  G02B6/12 ,  G02B6/12016 ,  G02B6/12021 ,  G02B6/12026

Abstract: A planar lightwave circuit includes an arrayed waveguide grating (AWG), with input and output waveguides, partially curved array waveguides with respective length differences, and planar waveguide regions for focusing optical energy between the input/output and array waveguides. Optimal waveguide widths and spacing along the planar waveguide region facets are disclosed, which are largely determinative of AWG size and optical performance. Also disclosed are optimal cross-sectional waveguide dimensions (e.g., width and height); modified index of refraction difference between the waveguide core and cladding regions; and optimal array waveguide lengths, path length differences, and free spectral range. These features, especially when combined with advanced fiber attachment, passivation and packaging techniques, result in high-yield, high-performance AWGs (both gaussian and flattop versions).

Abstract translation: 平面光波电路包括阵列波导光栅（AWG），其具有输入和输出波导，具有相应长度差的部分弯曲阵列波导和用于在输入/输出和阵列波导之间聚焦光能的平面波导区域。 公开了沿着平面波导区域面的最佳波导宽度和间距，其主要决定于AWG尺寸和光学性能。 还公开了最佳横截面波导尺寸（例如，宽度和高度）; 波导芯和包层区之间的折射率差异; 和最佳阵列波导长度，路径长度差和自由光谱范围。 这些特性，特别是结合先进的光纤附着，钝化和封装技术，可以获得高产出，高性能的AWG（高斯型和平板型）。

公开(公告)号：US06785148B1

公开(公告)日：2004-08-31

申请号：US09217401

申请日：1998-12-21

Applicant: Kenzo Ishida ,  Shuji Inoue ,  Kinya Ichikawa ,  Kenji Takahashi

Inventor： Kenzo Ishida ,  Shuji Inoue ,  Kinya Ichikawa ,  Kenji Takahashi

IPC: H05K710

CPC classification number: H05K3/325 ,  H01R12/52 ,  H01R13/2414 ,  H05K3/305 ,  H05K3/4069 ,  H05K7/1061 ,  H05K2201/0314 ,  H05K2201/10265 ,  H05K2201/10378

Abstract: A socket for mounting a processor and/or a board has a substrate with a built in socket. The socket has conductive, elastically deformable terminals. The socket may be mounted to a processor and a board without using conventional surface mount technology, instead providing a mechanical contact mechanism between the socket and the board or processor. An adhesive layer may also be used to connect the socket to a processor and/or a board.

Abstract translation: 用于安装处理器和/或板的插座具有带有内置插座的基板。 插座具有导电的，可弹性变形的端子。 插座可以安装到处理器和板上，而不使用传统的表面贴装技术，而是在插座和板或处理器之间提供机械接触机构。 也可以使用粘合剂层将插座连接到处理器和/或板。