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    Semiconductor device including nonvolatile memory having a floating gate electrode
    62.
    发明授权
    Semiconductor device including nonvolatile memory having a floating gate electrode 失效
    包括具有浮置栅电极的非易失性存储器的半导体器件

    公开(公告)号：US07626225B2

    公开(公告)日：2009-12-01

    申请号：US11422716

    申请日：2006-06-07

    Applicant: Susumu Inoue ,  Yutaka Maruo

    Inventor： Susumu Inoue ,  Yutaka Maruo

    IPC: H01L29/76

    CPC classification number: H01L29/7883 ,  H01L27/115 ,  H01L27/11558 ,  H01L29/66825

    Abstract: A semiconductor device including a nonvolatile memory element, the nonvolatile memory element, including: a first region, a second region formed adjacent to the first region, and a third region formed adjacent to the second region; the nonvolatile memory element further including a semiconductor layer, a separating insulation layer which is formed on the semiconductor layer and which demarcates a forming region of the nonvolatile memory element, a first diffusion layer which is formed on the semiconductor layer of the first region, a first source region and a first drain region formed on the first diffusion layer, a second diffusion layer which is separated from the first diffusion layer and which is formed on a periphery of the first diffusion layer and on the semiconductor layer of the second region, a second source region and a second drain region formed on the second diffusion layer, a third diffusion layer formed on the semiconductor layer of the third region, a first insulation layer formed above the semiconductor layer of the forming region of the nonvolatile memory element, and a first conductive layer formed above the first insulation layer.

    Abstract translation: 一种包括非易失性存储元件的半导体器件，所述非易失性存储元件包括：第一区域，与所述第一区域相邻形成的第二区域和与所述第二区域相邻形成的第三区域; 所述非易失性存储元件还包括半导体层，分隔绝缘层，其形成在所述半导体层上并且划分所述非易失性存储元件的形成区域;形成在所述第一区域的半导体层上的第一扩散层， 第一源极区域和形成在第一扩散层上的第一漏极区域，与第一扩散层分离并且形成在第一扩散层的周边和第二区域的半导体层上的第二扩散层， 第二源极区和形成在第二扩散层上的第二漏极区，形成在第三区的半导体层上的第三扩散层，形成在非易失性存储元件的形成区的半导体层上的第一绝缘层，以及 第一导电层形成在第一绝缘层之上。

    Semiconductor device
    63.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US07612396B2

    公开(公告)日：2009-11-03

    申请号：US11768387

    申请日：2007-06-26

    Applicant: Susumu Inoue ,  Yo Takeda ,  Yutaka Maruo

    Inventor： Susumu Inoue ,  Yo Takeda ,  Yutaka Maruo

    IPC: H01L31/062

    CPC classification number: H01L31/02164 ,  H01L23/552 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device includes a semiconductor element that is set up on a semiconductor layer, a light shielding wall that is set up around the semiconductor element, a hole that is set up on the light shielding wall, and a wiring layer that is electrically connected to the semiconductor element and is drawn out through the hole to the outside of the light shielding wall. The wiring layer has a pattern including a first part that is located within the hole and a second part that is located on the outside of the hole and has a larger width compared to the width of the first part, the width of the second part being the same with or larger than the width of the hole.

    NOVEL CRYSTALS OF PYRIMIDINE COMPOUND AND PROCESS FOR PRODUCING THE SAME
    64.
    发明申请
    NOVEL CRYSTALS OF PYRIMIDINE COMPOUND AND PROCESS FOR PRODUCING THE SAME 失效
    吡啶化合物的新型结晶及其制造方法

    公开(公告)号：US20090111986A1

    公开(公告)日：2009-04-30

    申请号：US12346544

    申请日：2008-12-30

    Applicant: Hitoshi HARADA ,  Hiroshi Ishihara ,  Yoshiaki Sato ,  Hiroyuki Chiba ,  Yuki Komatsu ,  Susumu Inoue ,  Naoki Ozeki

    Inventor： Hitoshi HARADA ,  Hiroshi Ishihara ,  Yoshiaki Sato ,  Hiroyuki Chiba ,  Yuki Komatsu ,  Susumu Inoue ,  Naoki Ozeki

    IPC: C07D405/14 ,  C07D405/02

    CPC classification number: C07D405/14 ,  C07D405/06

    Abstract: Crystals of 5-[2-amino-4-(2-furyl)pyrimidin-5-yl]-1-methylpyridin-2(1H)-one having a diffraction peak at a diffraction angle (2θ±0.2°) of 9.7° and/or 21.9° in a powder X-ray diffraction are suitable for an active ingredient of a preventing and therapeutic agent for diseases such as constipation. Crystals of 5-[2-amino-4-(2-furyl)pyrimidin-5-yl]-1-methylpyridin-2(1H)-one hydrate and amorphous 5-[2-amino-4-(2-furyl)pyrimidin-5-yl]-1-methylpyridin-2(1H)-one hydrate are also suitable for an active ingredient of a preventing and therapeutic agent for diseases such as constipation.

    Abstract translation: 在衍射角（2θ±0.2°）为9.7°的衍射峰的5- [2-氨基-4-（2-呋喃基）嘧啶-5-基] -1-甲基吡啶-2（1H） - 酮的晶体 和/或21.9°在粉末X射线衍射中适用于诸如便秘的疾病的预防和治疗剂的活性成分。 5- [2-氨基-4-（2-呋喃基）嘧啶-5-基] -1-甲基吡啶-2（1H） - 酮水合物和无定形的5- [2-氨基-4-（2-呋喃基） 嘧啶-5-基] -1-甲基吡啶-2（1H） - 酮水合物也适用于诸如便秘等疾病的预防和治疗剂的活性成分。

    Nonvolatile semiconductor memory device and control method thereof
    67.
    发明授权
    Nonvolatile semiconductor memory device and control method thereof 有权
    非易失性半导体存储器件及其控制方法

    公开(公告)号：US07142458B2

    公开(公告)日：2006-11-28

    申请号：US10929920

    申请日：2004-08-31

    Applicant: Susumu Inoue

    Inventor： Susumu Inoue

    IPC: G11C16/04

    CPC classification number: G11C16/3418 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3427

    Abstract: To provide a nonvolatile semiconductor memory device in which a disturb voltage onto a non-selected memory cell in writing operation is lessened, a nonvolatile semiconductor memory device, includes: a memory cell array equipped with a plurality of memory cells, a plurality of word lines, a plurality of bit lines, and a plurality of source lines; a word line control circuit to control the plurality of word lines; and a line control circuit to control the plurality of bit lines and the plurality of source lines. Each of the plurality of memory cells is equipped with a gate electrode, a first impurity region, a second impurity region, and an electron trap region, which is positioned between the gate electrode and a substrate, and is formed at least at the first impurity region side of both the first impurity region and second impurity region. At the time when a writing operation is performed for a selected memory cell, the word line control circuit provides a selected word line connected to the selected memory cell with a selection voltage, provides a non-selected word line with a first mis-erasing prevention voltage, and provides a source line that is not connected to the selected memory cell with a second mis-erasing prevention voltage.

    Abstract translation: 为了提供一种非易失性半导体存储器件，其中写入操作中的非选择存储单元上的干扰电压减小，非易失性半导体存储器件包括：配备有多个存储单元的存储单元阵列，多个字线 ，多个位线和多个源极线; 字线控制电路，用于控制所述多个字线; 以及线路控制电路，用于控制多个位线和多条源极线。 多个存储单元中的每一个配备有位于栅电极和基板之间的栅电极，第一杂质区，第二杂质区和电子陷阱区，并且至少形成在第一杂质 区域侧的第一杂质区域和第二杂质区域。 在对所选择的存储单元进行写入操作时，字线控制电路提供与选择的存储单元连接的所选择的字线和选择电压，从而提供未选择的字线，其具有第一防误删除功能 电压，并提供未连接到所选择的存储器单元的源极线，具有第二防止误擦除电压。

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