公开(公告)号：US20050224778A1

公开(公告)日：2005-10-13

申请号：US10819790

申请日：2004-04-07

Applicant: Valery Dubin ,  Swaminathan Sivakumar ,  Andrew Berlin ,  Mark Bohr

Inventor： Valery Dubin ,  Swaminathan Sivakumar ,  Andrew Berlin ,  Mark Bohr

IPC: H01L21/768 ,  H01L29/788 ,  H01L51/00 ,  H01L51/30

CPC classification number: H01L21/76838 ,  B82Y10/00 ,  H01L21/76852 ,  H01L51/0021 ,  H01L51/0048 ,  H01L51/0052 ,  H01L2221/1094 ,  Y10S977/742 ,  Y10S977/936

Abstract: A nano-electrode or nano-wire may be etched centrally to form a gap between nano-electrode portions. The portions may ultimately constitute a single electron transistor. The source and drain formed from the electrode portions are self-aligned with one another. Using spacer technology, the gap between the electrodes may be made very small.

Abstract translation: 可以将纳米电极或纳米线中心蚀刻以形成纳米电极部分之间的间隙。 这些部分可以最终构成单个电子晶体管。 由电极部分形成的源极和漏极彼此自对准。 使用间隔技术，可以使电极之间的间隙非常小。

公开(公告)号：US06927082B1

公开(公告)日：2005-08-09

申请号：US10797672

申请日：2004-03-10

Applicant: Swaminathan Sivakumar ,  Oleg Golonzka ,  Timothy F. Crimmins

Inventor： Swaminathan Sivakumar ,  Oleg Golonzka ,  Timothy F. Crimmins

IPC: H01L21/66

CPC classification number: H01L22/24

Abstract: Defective contact plug fills can be detected by applying an etching solution, which in some embodiments preferentially etches in the direction. The etching solution is some embodiments may also produce a characteristic type of undercutting underneath the contact plug fill. Contact plug fills with defects in them have undercutting underneath as a result of the etchant exposure, while defective contact plug fills have no such undercutting. The contact plug fills that are now undercut by etching exposure are unable to dissipate surface charge or surface applied potential and can be detected using voltage contrast methods or conventional electrical testing techniques, for example.

Abstract translation: 可以通过施加蚀刻溶液来检测接触塞填充不良，在一些实施例中蚀刻溶液优先在<111>方向蚀刻。 一些实施例的蚀刻溶液也可以产生在接触塞填充物下面的特征类型的底切。 接触塞填充缺陷，由于蚀刻剂暴露，底部有底切，而有缺陷的接触塞填充物没有这种底切。 例如，通过蚀刻曝光现在被切割的接触塞填充物不能消散表面电荷或表面施加电势，并且可以使用电压对比方法或常规电气测试技术来检测。

公开(公告)号：US20050148169A1

公开(公告)日：2005-07-07

申请号：US10749739

申请日：2003-12-30

Applicant: Rex Frost ,  Swaminathan Sivakumar

Inventor： Rex Frost ,  Swaminathan Sivakumar

IPC: G03F7/40 ,  H01L21/027 ,  H01L21/033 ,  H01L21/311 ,  H01L21/4763 ,  H01L21/768

CPC classification number: G03F7/40 ,  H01L21/0273 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76802

Abstract: The present invention relates to the reduction of critical dimensions and the reduction of feature sizes in manufacturing integrated circuits. Specifically, the method controls photoresist flow rates to develop critical dimensions beyond the resolution limits of the photoresist material used, and the limits of lithographic tool sets. The post exposure and developed resist pattern is exposed to a solvent prior to a bake or reflow process. Exposure to the solvent lowers the molecular weight of the resist material, modifying the resist material's reflow rate. The post-exposure resist is then easier to control during a subsequent reflow process to reduce the hole or line size of the patterned resist.

公开(公告)号：US20050081178A1

公开(公告)日：2005-04-14

申请号：US10682367

申请日：2003-10-08

Applicant: Swaminathan Sivakumar ,  Rex Frost ,  Phi Nguyen

Inventor： Swaminathan Sivakumar ,  Rex Frost ,  Phi Nguyen

IPC: G03F1/14 ,  G03F7/20 ,  G06F17/50

CPC classification number: G03F7/70466 ,  G03F1/70

Abstract: A mask pattern may be decomposed into two or more masks, each having a pitch greater than that of the original mask pattern. New, “partial-pattern” masks may be created for each of the new mask patterns. The original mask pattern is transferred to the photoresist for the corresponding layer using a multiple exposure technique in which the photoresist is exposed with each of the partial-pattern masks individually, e.g., back-to-back in a pass through a scanner, to define all of the features in the original pattern.

Abstract translation: 掩模图案可以分解成两个或更多个掩模，每个掩模的间距大于原始掩模图案的间距。 可以为每个新的掩模图案创建新的“部分图案”掩模。 使用多次曝光技术将原始掩模图案转印到用于相应层的光致抗蚀剂，其中光致抗蚀剂单独暴露于每个部分图案掩模，例如在通过扫描仪的通过中背靠背来定义 所有的功能在原来的模式。

公开(公告)号：US5933759A

公开(公告)日：1999-08-03

申请号：US778020

申请日：1996-12-31

Applicant: Phi L. Nguyen ,  Ralph A. Schweinfurth ,  Swaminathan Sivakumar

Inventor： Phi L. Nguyen ,  Ralph A. Schweinfurth ,  Swaminathan Sivakumar

IPC: H01L21/3065 ,  H01L21/308 ,  C03C15/00 ,  C03C25/06

CPC classification number: H01L21/3081 ,  H01L21/3065

Abstract: The present invention describes a method for forming submicron critical dimension shallow trenches with improved etch selectivity and etch bias control. In one embodiment of the present invention, three separate etch steps are performed. A polish stop layer (or an etch hard mask layer) and an oxide layer are etched during the first and second etch steps and the underlying substrate is etched during the third etch step. In the first etch step a carbon-fluorine based etchant is used in order to form a polymer layer along the photoresist, polish stop layer (or etch hard mask layer), and oxide layer. After the first etch step, a second etch step is used to remove the polymer from the horizontal surfaces of the semiconductor structures thereby forming polymer sidewalls as well as completing the etching of the polish stop layer (or etch hard mask layer) and the oxide layer. Polymer sidewalls protect the photoresist, polish stop layer (or etch hard mask layer), and oxide layer during the third etch step thereby improving the etch selectivity and etch bias control. The third etch step completes the formation of the trench by etching the substrate.

Abstract translation: 本发明描述了一种用于形成具有改进的蚀刻选择性和蚀刻偏压控制的亚微米临界尺寸的浅沟槽的方法。 在本发明的一个实施例中，执行三个单独的蚀刻步骤。 在第一和第二蚀刻步骤期间蚀刻抛光停止层（或蚀刻硬掩模层）和氧化物层，并且在第三蚀刻步骤期间蚀刻下面的衬底。 在第一蚀刻步骤中，为了沿着光致抗蚀剂，抛光停止层（或蚀刻硬掩模层）和氧化物层形成聚合物层，使用基于碳氟的蚀刻剂。 在第一蚀刻步骤之后，使用第二蚀刻步骤从半导体结构的水平表面去除聚合物，从而形成聚合物侧壁，以及完成抛光停止层（或蚀刻硬掩模层）的蚀刻和氧化物层 。 聚合物侧壁在第三蚀刻步骤期间保护光致抗蚀剂，抛光停止层（或蚀刻硬掩模层）和氧化物层，从而提高蚀刻选择性和蚀刻偏压控制。 第三蚀刻步骤通过蚀刻衬底完成沟槽的形成。