公开(公告)号：US06958547B2

公开(公告)日：2005-10-25

申请号：US10446749

申请日：2003-05-28

申请人： Valery M. Dubin ,  Chin-Chang Cheng ,  Makarem Hussein ,  Phi L. Nguyen ,  Ruth A. Brain

发明人： Valery M. Dubin ,  Chin-Chang Cheng ,  Makarem Hussein ,  Phi L. Nguyen ,  Ruth A. Brain

IPC分类号： H01L21/288 ,  H01L21/768 ,  H01L23/532 ,  H01L23/48

CPC分类号： H01L21/76843 ,  H01L21/288 ,  H01L21/76807 ,  H01L21/76838 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76864 ,  H01L21/76868 ,  H01L21/76874 ,  H01L21/76879 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： Multiple level interconnect structures and methods for fabricating the interconnect structures are disclosed. The interconnect structures may contain an interconnect line, an electrolessly deposited metal layer formed over the interconnect line, a via formed over the metal layer, and a second interconnect line formed over the via. Often the metal layer contains a cobalt or nickel alloy and provides an etch stop layer for formation of an opening corresponding to the via. The metal layer may provide protection to the underlying interconnect line and may replace a traditional protective dielectric layer. The metal layer is conductive, rather than dielectric, and provides a shunt for passage of electrical current between the via and the interconnect line. Similar metal layers may also be used within the interconnect structures as via liner layers and via plugs.

摘要翻译： 公开了用于制造互连结构的多级互连结构和方法。 互连结构可以包含互连线，在互连线上形成的无电沉积金属层，在金属层上形成的通孔，以及形成在通孔上的第二互连线。 通常，金属层含有钴或镍合金，并提供用于形成对应于通孔的开口的蚀刻停止层。 金属层可以为下面的互连线提供保护，并且可以代替传统的保护性介电层。 金属层是导电的，而不是电介质，并且提供用于通孔和互连线之间的电流的分流。 在互连结构中也可以使用类似的金属层，如通过衬垫层和通孔塞。

公开(公告)号：US07008872B2

公开(公告)日：2006-03-07

申请号：US10139052

申请日：2002-05-03

申请人： Valery M. Dubin ,  Chin-Chang Cheng ,  Makarem Hussein ,  Phi L. Nguyen ,  Ruth A. Brain

发明人： Valery M. Dubin ,  Chin-Chang Cheng ,  Makarem Hussein ,  Phi L. Nguyen ,  Ruth A. Brain

IPC分类号： H01L21/441

CPC分类号： H01L21/76843 ,  H01L21/288 ,  H01L21/76807 ,  H01L21/76838 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76864 ,  H01L21/76868 ,  H01L21/76874 ,  H01L21/76879 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： Multiple level interconnect structures and methods for fabricating the interconnect structures are disclosed. The interconnect structures may contain an interconnect line, an electrolessly deposited metal layer formed over the interconnect line, a via formed over the metal layer, and a second interconnect line formed over the via. Often the metal layer contains a cobalt or nickel alloy and provides an etch stop layer for formation of an opening corresponding to the via. The metal layer may provide protection to the underlying interconnect line and may replace a traditional protective dielectric layer. The metal layer is conductive, rather than dielectric, and provides a shunt for passage of electrical current between the via and the interconnect line. Similar metal layers may also be used within the interconnect structures as via liner layers and via plugs.

公开(公告)号：US06001699A

公开(公告)日：1999-12-14

申请号：US589903

申请日：1996-01-23

申请人： Phi L. Nguyen ,  Mark A. Fradkin ,  Gilroy J. Vandentop

发明人： Phi L. Nguyen ,  Mark A. Fradkin ,  Gilroy J. Vandentop

IPC分类号： H01L21/311 ,  H01L21/768 ,  C03C15/00

CPC分类号： H01L21/76802 ,  H01L21/31116

摘要： A method for forming contacts with vertical sidewalls, high aspect ratios, improved salicide and photoresist etch selectivity at submicron dimensions. In one currently preferred embodiment, an opening is formed in a dual oxide layer by etching the undoped oxide layer at a first rate and then etching the doped oxide layer at a second rate. The etch process is performed in a low density parallel plate reactor. The process parameters of the etch are fixed in ranges which optimize the etch process and allow greater control over the critical dimensions of the opening. For example, the oxide layer is etched at a pressure in the range of approximately 100-300 mTorr and with an etch chemistry having a CHF.sub.3 :CF.sub.4 gas flow ratio in the range of approximately 3:1-1:1, respectively.

摘要翻译： 用于在亚微米尺寸处形成具有垂直侧壁的接触的方法，高纵横比，改进的自对准硅化物和光致抗蚀剂蚀刻选择性。 在一个当前优选的实施例中，通过以第一速率蚀刻未掺杂的氧化物层，然后以第二速率蚀刻掺杂的氧化物层，在双重氧化物层中形成开口。 蚀刻工艺在低密度平行板反应器中进行。 蚀刻的工艺参数固定在优化蚀刻工艺并允许对开口的关键尺寸的更大控制的范围内。 例如，氧化物层在大约100-300mTorr的压力下蚀刻，并且蚀刻化学物质的CHF 3：CF 4气体流动比分别在大约3:1-1:1范围内。

公开(公告)号：US06472315B2

公开(公告)日：2002-10-29

申请号：US09808758

申请日：2001-03-14

申请人： Phi L. Nguyen ,  Lawrence D. Wong

发明人： Phi L. Nguyen ,  Lawrence D. Wong

IPC分类号： H01L214763

CPC分类号： H01L21/76802

摘要： A method for fabricating an interconnect system is provided. A low dielectric constant layer (LDCL) is formed onto a substrate. A hard mask is formed onto the LDCL. A patterning material is formed onto the hard mask. The patterning material is via patterned. A via pattern of the patterning material is transferred to the hard mask. The patterning material is stripped at a substantially low temperature. Vias are formed through the LDC using a via pattern formed in the hard mask.

摘要翻译： 提供一种用于制造互连系统的方法。 在基板上形成低介电常数层（LDCL）。 在LDCL上形成硬掩模。 在硬掩模上形成图形材料。 图案材料通过图案化。 图形材料的通孔图案被转印到硬掩模。 图案形成材料在基本上低的温度下被剥离。 通过使用形成在硬掩模中的通孔图案通过LDC形成通孔。

公开(公告)号：US5933759A

公开(公告)日：1999-08-03

申请号：US778020

申请日：1996-12-31

申请人： Phi L. Nguyen ,  Ralph A. Schweinfurth ,  Swaminathan Sivakumar

发明人： Phi L. Nguyen ,  Ralph A. Schweinfurth ,  Swaminathan Sivakumar

IPC分类号： H01L21/3065 ,  H01L21/308 ,  C03C15/00 ,  C03C25/06

CPC分类号： H01L21/3081 ,  H01L21/3065

摘要： The present invention describes a method for forming submicron critical dimension shallow trenches with improved etch selectivity and etch bias control. In one embodiment of the present invention, three separate etch steps are performed. A polish stop layer (or an etch hard mask layer) and an oxide layer are etched during the first and second etch steps and the underlying substrate is etched during the third etch step. In the first etch step a carbon-fluorine based etchant is used in order to form a polymer layer along the photoresist, polish stop layer (or etch hard mask layer), and oxide layer. After the first etch step, a second etch step is used to remove the polymer from the horizontal surfaces of the semiconductor structures thereby forming polymer sidewalls as well as completing the etching of the polish stop layer (or etch hard mask layer) and the oxide layer. Polymer sidewalls protect the photoresist, polish stop layer (or etch hard mask layer), and oxide layer during the third etch step thereby improving the etch selectivity and etch bias control. The third etch step completes the formation of the trench by etching the substrate.

摘要翻译： 本发明描述了一种用于形成具有改进的蚀刻选择性和蚀刻偏压控制的亚微米临界尺寸的浅沟槽的方法。 在本发明的一个实施例中，执行三个单独的蚀刻步骤。 在第一和第二蚀刻步骤期间蚀刻抛光停止层（或蚀刻硬掩模层）和氧化物层，并且在第三蚀刻步骤期间蚀刻下面的衬底。 在第一蚀刻步骤中，为了沿着光致抗蚀剂，抛光停止层（或蚀刻硬掩模层）和氧化物层形成聚合物层，使用基于碳氟的蚀刻剂。 在第一蚀刻步骤之后，使用第二蚀刻步骤从半导体结构的水平表面去除聚合物，从而形成聚合物侧壁，以及完成抛光停止层（或蚀刻硬掩模层）的蚀刻和氧化物层 。 聚合物侧壁在第三蚀刻步骤期间保护光致抗蚀剂，抛光停止层（或蚀刻硬掩模层）和氧化物层，从而提高蚀刻选择性和蚀刻偏压控制。 第三蚀刻步骤通过蚀刻衬底完成沟槽的形成。

公开(公告)号：US5843846A

公开(公告)日：1998-12-01

申请号：US775573

申请日：1996-12-31

申请人： Phi L. Nguyen ,  Ralph A. Schweinfurth

发明人： Phi L. Nguyen ,  Ralph A. Schweinfurth

IPC分类号： H01L21/306 ,  H01L21/302

CPC分类号： H01L21/30604

摘要： The present invention describes a method for rounding the top corners of a sub-micron trench in a semiconductor device directly after trench formation. In one embodiment of the present invention the etch process uses an etchant made up of a carbon-fluorine gas, an argon gas, and a nitrogen gas. The combination of gases enables the rounding of the top corners of the trench directly after the trench is formed. The combination of the carbon-fluorine and nitrogen gases etch back the silicon nitride and stress relief oxide layers in order to expose the top corners of the trench. As the top corners of the substrate are exposed the nitrogen and argon gases sputter the top corners rounding them as the etch process completes the trench.

摘要翻译： 本发明描述了一种用于在沟槽形成之后直接对半导体器件中的亚微米沟槽的顶角进行倒圆的方法。 在本发明的一个实施例中，蚀刻工艺使用由碳氟气体，氩气和氮气组成的蚀刻剂。 气体的组合使得能够在形成沟槽之后直接对沟槽的顶角进行四舍五入。 碳氟和氮气的组合会回蚀氮化硅和应力消除氧化物层，以暴露沟槽的顶角。 当衬底的顶角暴露时，随着蚀刻工艺完成沟槽，氮气和氩气溅射围绕它们的顶角。