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    Low noise graphene hall sensors, systems and methods of making and using same
    61.
    发明授权
    Low noise graphene hall sensors, systems and methods of making and using same 有权

    公开(公告)号：US10069065B2

    公开(公告)日：2018-09-04

    申请号：US14676233

    申请日：2015-04-01

    Applicant: Texas Instruments Incorporated

    Inventor： Arup Polley ,  Archana Venugopal ,  Robert Reid Doering ,  Luigi Colombo

    IPC: H01L43/10 ,  G01R33/07 ,  H01L43/06

    Abstract: Graphene Hall sensors, magnetic sensor systems and methods for sensing a magnetic field using an adjustable gate voltage to adapt the Hall sensor magnetic field sensitivity according to a control input for environmental or process compensation and/or real-time adaptation for balancing power consumption and minimum detectable field performance. The graphene Hall sensor gate voltage can be modulated and the sensor output signal can be demodulated to combat flicker or other low frequency noise. Also, graphene Hall sensors can be provided with capacitive coupled contacts for reliable low impedance AC coupling to instrumentation amplifiers or other circuits using integral capacitance.

    INTEGRATED CIRCUIT NANOPARTICLE THERMAL ROUTING STRUCTURE OVER INTERCONNECT REGION
    63.
    发明申请
    INTEGRATED CIRCUIT NANOPARTICLE THERMAL ROUTING STRUCTURE OVER INTERCONNECT REGION 审中-公开

    公开(公告)号：US20180151463A1

    公开(公告)日：2018-05-31

    申请号：US15361390

    申请日：2016-11-26

    Applicant: Texas Instruments Incorporated

    Inventor： Archana Venugopal ,  Benjamin Stassen Cook ,  Luigi Colombo ,  Robert Reid Doering

    IPC: H01L23/367 ,  H01L23/522 ,  H01L23/373 ,  H01L21/768

    Abstract: An integrated circuit has a thermal routing structure above a top interconnect level. The top interconnect level includes interconnects connected to lower interconnect levels, and does not include bond pads, probe pads, input/output pads, or a redistribution layer to bump bond pads. The thermal routing structure extends over a portion, but not all, of a plane of the integrated circuit containing the top interconnect level. The thermal routing structure includes a layer of nanoparticles in which adjacent nanoparticles are attached to each other. The layer of nanoparticles is free of an organic binder material. The thermal routing structure has a thermal conductivity higher than the metal in the top interconnect level. The layer of nanoparticles is formed by an additive process.

    SEMICONDUCTOR DEVICES WITH THERMOELECTRIC COOLER
    64.
    发明公开
    SEMICONDUCTOR DEVICES WITH THERMOELECTRIC COOLER 审中-公开

    公开(公告)号：US20240321677A1

    公开(公告)日：2024-09-26

    申请号：US18397476

    申请日：2023-12-27

    Applicant: Texas Instruments Incorporated

    Inventor： Jingjing Chen ,  Archana Venugopal

    IPC: H01L23/38 ,  H01L23/532 ,  H01L29/78

    CPC classification number: H01L23/38 ,  H01L23/53209 ,  H01L29/7824

    Abstract: Semiconductor devices including thermoelectric coolers and method of operating the semiconductor devices are described. A semiconductor device includes an SOI substrate with one or more components (e.g., a transistor) generating heat during operation. The semiconductor device includes a thermoelectric cooler surrounding the transistor. The thermoelectric cooler includes a first electrode laterally surrounding the transistor, a holey silicon region laterally surrounding and contacting the first electrode, and a second electrode laterally surrounding and contacting the holey silicon region. The thermoelectric cooler, when activated, can reduce operating temperature of the transistor. In some cases, pre-cooling may be done to further reduce the operating temperature.

    Integration of graphene and boron nitride hetero-structure device
    68.
    发明授权
    Integration of graphene and boron nitride hetero-structure device 有权

    公开(公告)号：US11081593B2

    公开(公告)日：2021-08-03

    申请号：US16661758

    申请日：2019-10-23

    Applicant: Texas Instruments Incorporated

    Inventor： Archana Venugopal ,  Luigi Colombo

    IPC: H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L29/20 ,  H01L29/267 ,  H01L29/49 ,  H01L29/45 ,  H01L29/16 ,  H01L29/778

    Abstract: A microelectronic device includes a gated graphene component. The gated graphene component has a graphitic layer containing one or more layers of graphene. The graphitic layer has a channel region, a first contact region adjacent to the channel region and a second contact region adjacent to the channel region. A patterned hexagonal boron nitride (hBN) layer is disposed on the graphitic layer above the channel region. A gate is located over the patterned hBN layer above the channel region. A first connection is disposed on the graphitic layer in the first contact region, and a second connection is disposed on the graphitic layer in the second contact region. The patterned hBN layer does not extend completely under the first connection or under the second connection. A method of forming the gated graphene component in the microelectronic device is disclosed.

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