摘要:
Methods and apparatus provide for sending a data command from a first of a plurality of devices to a first address concentrator within a first of a plurality of processing systems; selecting one of the other processing systems, the selected processing system having data addressed by the data command stored therein; sending the data command to a first address concentrator of the selected processing system; and broadcasting the data command from the first address concentrator of the selected processing system to a second address concentrator in each of the processing systems.
摘要:
A cooling system has a configuration in which a cooling system for an inverter device and a motor generator also serves as a cooling system for a battery. In this configuration, a control device performs temperature-raising control of the battery when a battery temperature is below a prescribed temperature lower limit value. The control device controls an operation of a switching valve such that cooling water from a cooling medium path is outputted to a bypass path. Further, if a cooling water temperature is lower than a prescribed temperature, the control device controls the inverter device such that a power loss during a switching operation in a switching element included in the inverter device becomes larger than a power loss during normal control. As a result, the cooling system having a small-sized, low-cost configuration rapidly recovers capacity decline of the battery, which occurs at low temperatures.
摘要:
A downstream port 22 of a bridge 20 connecting a processor unit and a peripheral device acknowledges access from the peripheral device via one of a plurality of downstream channels available for access by the peripheral device to a memory of the processor unit, the downstream channels being virtual channels provided for interfacing with the peripheral device. The router 24 routes the access to upstream channels each assigned a memory bandwidth available for access to the memory, the upstream channels being virtual channels supported by the processor unit. In this process, the router refers to a table storing identifiers of the downstream channels and identifiers of the upstream channels in association with each other so as to allocate to the peripheral device the upstream channel corresponding to the downstream channel used by the peripheral device, in response to the access from the peripheral device.
摘要:
Brushless motor (1) which is an electric motor, is provided with a stator unit (3) inserted in and engaged with case (2). A part of the coating material (21) for coating the coil (17) of the stator unit (3) enters the receiving part (13) formed in the bottom part (2B) of the case (2); and the bottom part (2B) of the case (2) and the coil (17) are linked by this coating material (21). While coating, the coating material (21) is dripped from the opening side of the case (2) with the stator unit (3) in the inserted condition in the case (2).
摘要:
Disclosed is a traffic distribution device, which is used in a way that connects to a 0-th network, a first network including one or more servers and to a second network connected to the first network and including M-pieces of high-order layer processing devices associated with 0 through M-1, capable of improving a throughput of a network without changing a server sided default gateway address. The traffic distribution device has first packet relay unit translating a packet containing a predetermined destination IP address from the 0-th network into a packet in which a destination MAC address is set as a first network sided MAC address of the high-order layer processing device, which MAC address is associated with a remainder value obtained by dividing a source IP address of the packet by M, and transmitting this packet onto the first network; and second packet relay unit translating the packet from the second network into a packet in which a destination MAC address is a second network sided MAC address of the high-order layer processing device, which MAC address is associated with a remainder value obtained by dividing the destination IP address of the packet by M, and transmitting this packet onto the second network.
摘要:
A method, an apparatus, and a computer program product are provided for completing a plurality of (direct memory access) DMA commands in a computer system. It is determined whether the DMA commands are chained together as a list DMA command. Upon a determination that the DMA commands are chained together as a list DMA command, it is also determined whether a current list element of the list DMA command is fenced. Upon a determination that the current list element is not fenced, a next list element is fetched and processed before the current list element has been completed.
摘要:
Method and apparatus are provided for improved connection of devices and lower latency of communications between devices of a massively parallel network. In particular, method and apparatus are provided for cross-bar switches, a multiple protocol interface device, a low latency upper communication protocol layer, addressing and remote direct memory access over a massively parallel network.
摘要:
The issuance timing of commands received from and transmitted to among a plurality of processing units is controlled efficiently. An execution command storage unit 222 stores execution commands, received from an external command transmitting entity, where a predetermined upper-limit number of execution commands to be stored is set. An execution command issuing unit 230 retrieves the execution commands stored and issues them to a command execution entity. An adjustment command storage unit 224 stores the adjustment command, transmitted from the command transmitting entity, to adjust the issuance order of the execution commands. A storage area for storing the execution commands to be stored in the execution command storage unit 222 and a storage area for storing the adjustment command to be stored in the adjustment command storage unit 224 are separately provided. When the adjustment command is stored, the execution command issuing unit 230 issues an execution command received after the reception of the adjustment command, on the condition that the issuance of execution commands received prior to the reception of the adjustment command has been completed.
摘要:
A method is provided for executing a plurality of parallel executable sequences of instructions on a processor having a plurality of execution units operated by a single instruction unit. The method includes a) detecting a plurality of sequences of instructions adapted for parallel execution from instructions being provided to the processor, wherein each sequence is adapted for execution by a subset of the plurality of execution units and b) storing information representing a stall status of the execution units. Then, a step c) is performed, wherein, for each unexecuted sequence of the plurality of sequences: i) all of the plurality of execution units other than the subset which corresponds to the unexecuted sequence are stalled, and ii) the sequence of instructions is executed by the corresponding subset. Thereafter, it is determined in a step d) whether a current stall status of the plurality of execution units matches the stall status represented by the stored information. When there is no match, the steps b) through d) are repeated until there is a match in which the current stall status represented by the stored information matches the stored information.
摘要:
The present invention has been conceived in view of the above described situation, and an object of the invention is to provide an information processing device, data transfer method and information storage medium that can commence data transfer to an I/O device immediately, and can stably exhibit data transfer performance. In an information processing device provided with hardware for sharing an address translation table, for translating logical addresses of a memory to physical addresses, between a main processor and a sub-processor, one of the sub-processors is caused to function as means for receiving a transfer request designating a logical address of the memory, means for translating the logical address that has been designated in the transfer request to a physical address using the shared address translation table, and means for executing transfer processing for data stored in the memory 14 according to the translated physical address.