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    Gate Structures for Stacked Semiconductor Devices
    62.
    发明申请
    Gate Structures for Stacked Semiconductor Devices 有权

    公开(公告)号：US20230062940A1

    公开(公告)日：2023-03-02

    申请号：US17461329

    申请日：2021-08-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Mrunal Abhijith KHADERBAD ,  Sathaiya Mahaveer Dhanyakumar ,  Huicheng Chang ,  Keng-Chu Lin

    IPC: H01L27/092 ,  H01L21/8238

    Abstract: The present disclosure describes a semiconductor device and methods for forming the same. The semiconductor device includes a first transistor device of a first type and a second transistor device of a second type. The first transistor device includes first nanostructures, a first pair of source/drain structures, and a first gate structure on the first nanostructures. The second transistor device of a second type is formed over the first transistor device. The second transistor device includes second nanostructures over the first nanostructures, a second pair of source/drain structures over the first pair or source/drain structures, and a second gate structure on the second nanostructures and over the first nanostructures. The semiconductor device further includes a first isolation structure in contact with the first and second nanostructures and a second isolation structure in contact with a top surface of the first pair of source/drain structures.

    CONTACT STRUCTURE FOR SEMICONDUCTOR DEVICE
    63.
    发明申请
    CONTACT STRUCTURE FOR SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20230008496A1

    公开(公告)日：2023-01-12

    申请号：US17371288

    申请日：2021-07-09

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Mrunal Abhijith Khaderbad ,  Keng-Chu Lin ,  Ko-Feng Chen ,  Yu-Yun Peng

    IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L21/8234

    Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, first and second contact structures proximate to each other and over the substrate, and first and second dielectric layers formed over the first and second contact structures, respectively. A top portion of the first dielectric layer can include a first dielectric material. A bottom portion of the first dielectric layer can include a second dielectric material different from the first dielectric material. The second dielectric layer can include a third dielectric material different from the first dielectric material.

    Semiconductor device and manufacturing method thereof
    64.
    发明授权
    Semiconductor device and manufacturing method thereof 有权

    公开(公告)号：US11522074B2

    公开(公告)日：2022-12-06

    申请号：US17200226

    申请日：2021-03-12

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Kuo-Cheng Ching ,  Kuan-Lun Cheng ,  Chih-Hao Wang ,  Keng-Chu Lin ,  Shi-Ning Ju

    IPC: H01L27/088 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02

    Abstract: A semiconductor device includes a substrate, a first semiconductor fin, a second semiconductor fin, a gate structure, a plurality of source/drain structures, a shallow trench isolation (STI) oxide, and a dielectric layer. The first semiconductor fin extends upwardly from the substrate. The second semiconductor fin extends upwardly from the substrate. The gate structure extends across the first and second semiconductor fins. The source/drain structures are on the first and second semiconductor fins. The STI oxide extends continuously between the first and second semiconductor fins and has a U-shaped profile when viewed in a cross section taken along a lengthwise direction of the gate structure. The dielectric layer is partially embedded in the STI oxide and has a U-shaped profile when viewed in the cross section taken along the lengthwise direction of the gate structure.

    Low Resistance Fill Metal Layer Material as Stressor in Metal Gates
    65.
    发明申请
    Low Resistance Fill Metal Layer Material as Stressor in Metal Gates 有权

    公开(公告)号：US20220384439A1

    公开(公告)日：2022-12-01

    申请号：US17870964

    申请日：2022-07-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Mrunal A Khaderbad ,  Ziwei Fang ,  Keng-Chu Lin ,  Hsueh Wen Tsau

    IPC: H01L27/092 ,  H01L21/8234 ,  H01L21/8238

    Abstract: An integrated circuit (IC) device includes a semiconductor substrate having a first plurality of stacked semiconductor layers in a p-type transistor region and a second plurality of stacked semiconductor layers in a n-type transistor region. A gate dielectric layer wraps around each of the first and second plurality of stacked semiconductor layers. A first metal gate in the p-type transistor region has a work function metal layer and a first fill metal layer, where the work function metal layer wraps around and is in direct contact with the gate dielectric layer and the first fill metal layer is in direct contact with the work function metal layer. A second metal gate in the n-type transistor region has a second fill metal layer that is in direct contact with the gate dielectric layer, where the second fill metal layer has a work function about equal to or lower than 4.3 eV.

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