公开(公告)号：US12148807B2

公开(公告)日：2024-11-19

申请号：US17371245

申请日：2021-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hung Chu ,  Ding-Kang Shih ,  Keng-Chu Lin ,  Pang-Yen Tsai ,  Sung-Li Wang ,  Shuen-Shin Liang ,  Tsungyu Hung ,  Hsu-Kai Chang

IPC: H01L29/417 ,  H01L21/285 ,  H01L29/40 ,  H01L29/423

Abstract: The present disclosure describes a method to form a semiconductor device with backside contact structures. The method includes forming a semiconductor device on a first side of a substrate. The semiconductor device includes a source/drain (S/D) region. The method further includes etching a portion of the S/D region on a second side of the substrate to form an opening and forming an epitaxial contact structure on the S/D region in the opening. The second side is opposite to the first side. The epitaxial contact structure includes a first portion in contact with the S/D region in the opening and a second portion on the first portion. A width of the second portion is larger than the first portion.

公开(公告)号：US11581259B2

公开(公告)日：2023-02-14

申请号：US16950537

申请日：2020-11-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei Chang ,  Chien-Shun Liao ,  Sung-Li Wang ,  Shuen-Shin Liang ,  Shu-Lan Chang ,  Yi-Ying Liu ,  Chia-Hung Chu ,  Hsu-Kai Chang

IPC: H01L23/532 ,  H01L23/528 ,  H01L21/768

Abstract: The present disclosure describes a method for the fabrication of ruthenium conductive structures over cobalt conductive structures. In some embodiments, the method includes forming a first opening in a dielectric layer to expose a first cobalt contact and filling the first opening with ruthenium metal to form a ruthenium contact on the first cobalt contact. The method also includes forming a second opening in the dielectric layer to expose a second cobalt contact and a gate structure and filling the second opening with tungsten to form a tungsten contact on the second cobalt contact and the gate structure. Further, the method includes forming a copper conductive structure on the ruthenium contact and the tungsten contact, where the copper from the copper conductive structure is in contact with the ruthenium metal from the ruthenium contact.

公开(公告)号：US20230378305A1

公开(公告)日：2023-11-23

申请号：US18227731

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Li WANG ,  Hsu-Kai Chang ,  Jhih-Rong Huang ,  Yen-Tien Tung ,  Chia-Hung Chu ,  Tzer-Min Shen ,  Pinyen Lin

IPC: H01L29/45 ,  H01L21/285 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/45 ,  H01L21/28518 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7851 ,  H01L21/823418 ,  H01L29/7839

Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure disposed on the substrate, a gate structure disposed on the fin structure, a source/drain (S/D) region disposed adjacent to the gate structure, a contact structure disposed on the S/D region, and a dipole layer disposed at an interface between the ternary compound layer and the S/D region. The contact structure includes a ternary compound layer disposed on the S/D region, a work function metal (WFM) silicide layer disposed on the ternary compound layer, and a contact plug disposed on the WFM silicide layer.

公开(公告)号：US11767336B2

公开(公告)日：2023-09-26

申请号：US17870324

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsu-Kai Chang ,  Chi-Ming Yang ,  Jui-Hsiung Liu ,  Jui-Hung Fu ,  Hsin-Yi Wu

IPC: C07F7/22 ,  G03F7/004 ,  G03F7/36 ,  G03F7/20 ,  G03F7/32 ,  G03F7/30

CPC classification number: C07F7/2224 ,  G03F7/0042 ,  G03F7/30 ,  G03F7/36 ,  G03F7/2004 ,  G03F7/325

Abstract: The present disclosure is directed to organotin cluster compounds having formula (I) and their use as photoresists in extreme ultraviolet lithography processes.

公开(公告)号：US20230246082A1

公开(公告)日：2023-08-03

申请号：US18297854

申请日：2023-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hung Chu ,  Tsungyu Hung ,  Hsu-Kai Chang ,  Ding-Kang Shih ,  Keng-Chu Lin ,  Pang-Yen Tsai ,  Sung-Li Wang ,  Shuen-Shin Liang

IPC: H01L29/417 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786 ,  H01L21/02 ,  H01L21/285

CPC classification number: H01L29/41733 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66742 ,  H01L29/78696 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/28518 ,  H01L29/78618

Abstract: A semiconductor device structure according to the present disclosure includes a source feature and a drain feature, at least one channel structure extending between the source feature and the drain feature, a gate structure wrapped around each of the at least one channel structure, a semiconductor layer over the gate structure, a dielectric layer over the semiconductor layer, a doped semiconductor feature extending through the semiconductor layer and the dielectric layer to be in contact with the source feature, a metal contact plug over the doped semiconductor feature, and a buried power rail disposed over the metal contact plug.

公开(公告)号：US11594609B2

公开(公告)日：2023-02-28

申请号：US16887577

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing, Co., Ltd.

Inventor： Shuen-Shin Liang ,  Chun-I Tsai ,  Chih-Wei Chang ,  Chun-Hsien Huang ,  Hung-Yi Huang ,  Keng-Chu Lin ,  Ken-Yu Chang ,  Sung-Li Wang ,  Chia-Hung Chu ,  Hsu-Kai Chang

IPC: H01L29/45 ,  H01L23/535 ,  H01L21/768

Abstract: The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes forming a liner-free conductive structure on a cobalt conductive structure disposed on a substrate, depositing a cobalt layer on the liner-free conductive structure and exposing the liner-free conductive structure to a heat treatment. The method further includes removing the cobalt layer from the liner-free conductive structure.

公开(公告)号：US11521929B2

公开(公告)日：2022-12-06

申请号：US17141445

申请日：2021-01-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shuen-Shin Liang ,  Chun-I Tsai ,  Chih-Wei Chang ,  Chun-Hsien Huang ,  Hung-Yi Huang ,  Keng-Chu Lin ,  Ken-Yu Chang ,  Sung-Li Wang ,  Chia-Hung Chu ,  Hsu-Kai Chang

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L21/285

Abstract: The present disclosure describes a method for forming capping layers configured to prevent the migration of out-diffused cobalt atoms into upper metallization layers In some embodiments, the method includes depositing a cobalt diffusion barrier layer on a liner-free conductive structure that includes ruthenium, where depositing the cobalt diffusion barrier layer includes forming the cobalt diffusion barrier layer self-aligned to the liner-free conductive structure. The method also includes depositing, on the cobalt diffusion barrier layer, a stack with an etch stop layer and dielectric layer, and forming an opening in the stack to expose the cobalt diffusion barrier layer. Finally, the method includes forming a conductive structure on the cobalt diffusion barrier layer.

公开(公告)号：US20240371952A1

公开(公告)日：2024-11-07

申请号：US18770393

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hung CHU ,  Tsungyu Hung ,  Hsu-Kai Chang ,  Ding-Kang Shih ,  Keng-Chu Lin ,  Pang-Yen Tsai ,  Sung-Li Wang ,  Shuen-Shin Liang

IPC: H01L29/417 ,  H01L21/285 ,  H01L29/40 ,  H01L29/423

Abstract: The present disclosure describes a method to form a semiconductor device with backside contact structures. The method includes forming a semiconductor device on a first side of a substrate. The semiconductor device includes a source/drain (S/D) region. The method further includes etching a portion of the S/D region on a second side of the substrate to form an opening and forming an epitaxial contact structure on the S/D region in the opening. The second side is opposite to the first side. The epitaxial contact structure includes a first portion in contact with the S/D region in the opening and a second portion on the first portion. A width of the second portion is larger than the first portion.

公开(公告)号：US12046634B2

公开(公告)日：2024-07-23

申请号：US18158148

申请日：2023-01-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei Chang ,  Shuen-Shin Liang ,  Sung-Li Wang ,  Hsu-Kai Chang ,  Chia-Hung Chu ,  Chien-Shun Liao ,  Yi-Ying Liu

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/0665 ,  H01L29/1033 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66742

Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and methods of fabricating the same are disclosed. The semiconductor device includes first and second S/D regions, a nanostructured channel region disposed between the first and second S/D regions, a gate structure surrounding the nanostructured channel region, first and second contact structures disposed on first surfaces of the first and second S/D regions, a third contact structure disposed on a second surface of the first S/D region, and an etch stop layer disposed on a second surface of the second S/D region. The third contact structure includes a metal silicide layer, a silicide nitride layer disposed on the metal silicide layer, and a conductive layer disposed on the silicide nitride layer.

公开(公告)号：US11894437B2

公开(公告)日：2024-02-06

申请号：US17320553

申请日：2021-05-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shuen-Shin Liang ,  Chih-Chien Chi ,  Chien-Shun Liao ,  Keng-Chu Lin ,  Kai-Ting Huang ,  Sung-Li Wang ,  Yi-Ying Liu ,  Chia-Hung Chu ,  Hsu-Kai Chang ,  Cheng-Wei Chang

IPC: H01L29/45 ,  H01L23/535 ,  H01L23/532 ,  H01L29/78 ,  H01L21/768

CPC classification number: H01L29/45 ,  H01L21/7684 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76882 ,  H01L21/76895 ,  H01L23/535 ,  H01L23/53209 ,  H01L29/7851

Abstract: The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.