公开(公告)号：US11289580B2

公开(公告)日：2022-03-29

申请号：US16902072

申请日：2020-06-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Georgios Vellianitis

IPC: H01L21/00 ,  H01L29/00 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/51 ,  H01L21/762

Abstract: In a method of manufacturing a semiconductor device, a single crystal oxide layer is formed over a substrate. After the single crystal oxide layer is formed, an isolation structure to define an active region is formed. A gate structure is formed over the single crystal oxide layer in the active region. A source/drain structure is formed.

公开(公告)号：US11264498B2

公开(公告)日：2022-03-01

申请号：US16901004

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Gerben Doornbos ,  Blandine Duriez ,  Georgios Vellianitis ,  Marcus Johannes Henricus Van Dal ,  Mauricio Manfrini

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/11587 ,  H01L27/1159

Abstract: A semiconductor device includes a semiconductor substrate, a first source region, a first drain region, a first gate, a second source region, a second drain region, a second gate, and a first dielectric layer. The first source region and the first drain region are disposed within the semiconductor substrate. The first gate is disposed over the semiconductor substrate in between the first source region and the first drain region. The second source region and the second drain region are disposed within the semiconductor substrate. The second gate is disposed over the semiconductor substrate in between the second source region and the second drain region. The first dielectric layer is located in between the first gate and the semiconductor substrate, and in between the second gate and the semiconductor substrate, wherein the first dielectric layer extends from a position below the first gate to a position below the second gate.

公开(公告)号：US20210399097A1

公开(公告)日：2021-12-23

申请号：US17086644

申请日：2020-11-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Georgios Vellianitis

IPC: H01L29/221 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor channel layer, a gate structure, complex regions, a source terminal and a drain terminal. The gate structure is disposed on the semiconductor channel layer. The source terminal and the drain terminal are disposed on the semiconductor channel layer. The complex regions ae respectively disposed between the source terminal and the semiconductor channel layer and between the drain terminal and the semiconductor channel layer.

公开(公告)号：US20210328068A1

公开(公告)日：2021-10-21

申请号：US17361141

申请日：2021-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Blandine Duriez ,  Marcus Johannes Henricus Van Dal ,  Martin Christopher Holland ,  Gerben Doornbos ,  Georgios Vellianitis

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L21/268 ,  H01L21/285 ,  H01L21/324 ,  H01L21/311

Abstract: A method of forming a semiconductor device includes forming source/drain contact openings extending through at least one dielectric layer to expose source/drain contact regions of source/drain structures. The method further includes forming conductive plugs in the source/drain contact openings. The method further includes depositing a light blocking layer over the conductive plugs and the at least one dielectric layer. The method further includes etching the light blocking layer to expose the conductive plugs. The method further includes directing a laser irradiation to the conductive plugs and the light blocking layer. The laser irradiation is configured to activate dopants in the source/drain contact regions.

公开(公告)号：US20210125986A1

公开(公告)日：2021-04-29

申请号：US16801071

申请日：2020-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Georgios Vellianitis

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/06

Abstract: A complementary metal-oxide-semiconductor device includes a p-type field effect transistor and an n-type filed effect transistor. The p-type filed effect transistor has a first transistor architecture. The n-type field effect transistor is coupled with the p-type field effect transistor and has a second transistor architecture. The second transistor architecture is different from the first transistor architecture. The p-type field effect transistor and the n-type field effect transistor share a same gate structure.

公开(公告)号：US10978557B2

公开(公告)日：2021-04-13

申请号：US16449611

申请日：2019-06-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Martin Christopher Holland ,  Mark Van Dal ,  Georgios Vellianitis ,  Blandine Duriez ,  Gerben Doornbos

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/165 ,  H01L29/04 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/40 ,  H01L29/786

Abstract: A method includes forming a plurality of first semiconductor layers and second semiconductor layers in an alternate manner over a substrate; etching the first semiconductor layers and second semiconductor layers to form a fin structure, in which the fin structure comprises a plurality of first nanowires and second nanowires alternately arranged, the first nanowires have respective remaining portions of the first semiconductor layers, and the second nanowires have respective remaining portions of second semiconductor layers; forming a dummy gate over the fin structure; forming a plurality of gate spacers on opposite sidewalls of the dummy gate, respectively; replacing the dummy gate with a metal gate; removing first portions of the second nanowires exposed by the metal gate and metal gate and the gate spacers suspended; and forming an epitaxy layer wrapping around the first portions of the first nanowires, in which opposite sidewalls of the epitaxy layer have zig-zag contour.

公开(公告)号：US10672889B2

公开(公告)日：2020-06-02

申请号：US15988496

申请日：2018-05-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Georgios Vellianitis

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/308 ,  H01L21/8258 ,  H01L27/092 ,  H01L21/762

Abstract: A method of manufacturing a semiconductor device includes forming an isolation region on a semiconductor substrate. A trench is formed in an crystallographic direction of the semiconductor substrate in the isolation region. An epitaxial layer is grown in the trench. The epitaxial layer is patterned to form a semiconductor fin orientated along an crystallographic direction of the semiconductor substrate, wherein ≠ .

公开(公告)号：US10522623B1

公开(公告)日：2019-12-31

申请号：US15998683

申请日：2018-08-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Martin Christopher Holland ,  Georgios Vellianitis

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78

Abstract: Provided herein are semiconductor structures that include germanium and have a germanium nitride layer on the surface, as well as methods of forming the same. The described structures include nanowires and fins. Methods of the disclosure include metal-organic chemical vapor deposition with a germanium precursor. The described methods also include using a N2H4 vapor.

公开(公告)号：US09406517B2

公开(公告)日：2016-08-02

申请号：US13794914

申请日：2013-03-12

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Georgios Vellianitis

IPC: H01L29/165 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/267

CPC classification number: H01L21/28255 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/267 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present disclosure relates to a transistor device having a germanium cap layer that is able to provide for a low interface trap density, while meeting effective oxide thickness scaling requirements, and a related method of fabrication. In some embodiments, the disclosed transistor device has a channel layer disposed within a semiconductor body at a location between a source region and a drain region. A germanium cap layer is disposed onto the channel layer. A gate dielectric layer is separated from the channel layer by the germanium cap layer, and a gate region is disposed above the gate dielectric layer. Separating the gate dielectric layer from the channel layer allows for the germanium cap layer to prevent diffusion of atoms from the channel layer into the gate dielectric layer, thereby provide for a low interface trap density.

Abstract translation: 本公开涉及具有锗盖层的晶体管器件，其能够提供低界面陷阱密度，同时满足有效的氧化物厚度缩放要求，以及相关的制造方法。 在一些实施例中，所公开的晶体管器件具有在源极区域和漏极区域之间的位置处设置在半导体主体内的沟道层。 锗覆盖层设置在沟道层上。 栅极电介质层通过锗覆盖层与沟道层分离，并且栅极区域设置在栅极介电层的上方。 将栅极介电层与沟道层分离允许锗覆盖层防止原子从沟道层扩散到栅极介电层中，从而提供低的界面陷阱密度。