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    Semiconductor device and method of forming same
    62.
    发明授权
    Semiconductor device and method of forming same 有权

    公开(公告)号：US11145728B2

    公开(公告)日：2021-10-12

    申请号：US16809876

    申请日：2020-03-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

    IPC: H01L29/417 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L21/311

    Abstract: A method includes forming a gate structure over a fin protruding above a substrate, forming a gate spacer layer on sidewalls of the gate structure, forming an etch stop layer on sidewalls of the gate spacer layer, replacing the gate structure with a gate stack, forming a source/drain contact adjacent the etch stop layer, recessing the gate stack to form a first recess, filling the first recess with a first dielectric material, recessing the source/drain contact and the etch stop layer to form a second recess, filling the second recess with a second dielectric material, recessing the second dielectric material and the gate spacer layer to form a third recess, and filling the third recess with a third dielectric material, wherein the composition of the third dielectric material is different from that of the first dielectric material and the second dielectric material.

    USING A LINER LAYER TO ENLARGE PROCESS WINDOW FOR A CONTACT VIA
    64.
    发明申请
    USING A LINER LAYER TO ENLARGE PROCESS WINDOW FOR A CONTACT VIA 有权

    公开(公告)号：US20210280454A1

    公开(公告)日：2021-09-09

    申请号：US16808902

    申请日：2020-03-04

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Li-Zhen Yu ,  Cheng-Chi Chuang ,  Chih-Hao Wang ,  Yu-Ming Lin ,  Lin-Yu Huang

    IPC: H01L21/768 ,  H01L23/522 ,  H01L29/417 ,  H01L29/66

    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a substrate, a first contact layer, and a gate electrode. The first contact layer overlies the substrate and the gate electrode overlies the substrate and is laterally spaced from the first contact layer. A first spacer structure surrounds outermost sidewalls of the first contact layer and separates the gate electrode from the first contact layer. A first hard mask structure is arranged over the first contact layer and is between portions of the first spacer structure. A first contact via extends through the first hard mask structure and contacts the first contact layer. A first liner layer is arranged directly between the first hard mask structure and the first spacer structure.

    Semiconductor device and method for manufacturing the same
    67.
    发明授权
    Semiconductor device and method for manufacturing the same 有权

    公开(公告)号：US11037824B2

    公开(公告)日：2021-06-15

    申请号：US16999997

    申请日：2020-08-21

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Jia-Chuan You ,  Chia-Hao Chang ,  Wei-Hao Wu ,  Yu-Ming Lin ,  Chih-Hao Wang

    IPC: H01L21/768 ,  H01L29/66 ,  H01L21/28 ,  H01L21/311 ,  H01L23/522 ,  H01L21/033

    Abstract: A semiconductor device includes a substrate, a gate stack, a first gate spacer and a second gate spacer, a first source/drain region and a second source/drain region, a first conductive feature and a second conductive feature, and a first contact plug and a second contact plug. The first conductive feature and the second conductive feature are over the first source/drain region and the second source/drain region, respectively. The first conductive cap and the second conductive cap are over the first conductive feature and the second conductive feature, respectively. The first contact plug and the second contact plug are over the first conductive cap and the second conductive cap, respectively, in which the first contact plug is separated from the first gate spacer, and the second contact plug is in contact with a sidewall and a top surface of the second gate spacer.

    SEMICONDUCTOR DEVICE AND METHOD OF FORMING SAME
    69.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FORMING SAME 有权

    公开(公告)号：US20210134969A1

    公开(公告)日：2021-05-06

    申请号：US16809876

    申请日：2020-03-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

    IPC: H01L29/417 ,  H01L29/78 ,  H01L29/08 ,  H01L21/311 ,  H01L29/66

    Abstract: A method includes forming a gate structure over a fin protruding above a substrate, forming a gate spacer layer on sidewalls of the gate structure, forming an etch stop layer on sidewalls of the gate spacer layer, replacing the gate structure with a gate stack, forming a source/drain contact adjacent the etch stop layer, recessing the gate stack to form a first recess, filling the first recess with a first dielectric material, recessing the source/drain contact and the etch stop layer to form a second recess, filling the second recess with a second dielectric material, recessing the second dielectric material and the gate spacer layer to form a third recess, and filling the third recess with a third dielectric material, wherein the composition of the third dielectric material is different from that of the first dielectric material and the second dielectric material.

    Source/drain isolation structure and methods thereof
    70.
    发明授权
    Source/drain isolation structure and methods thereof 有权

    公开(公告)号：US10755964B1

    公开(公告)日：2020-08-25

    申请号：US16427594

    申请日：2019-05-31

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Lin-Yu Huang ,  Sheng-Tsung Wang ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

    IPC: H01L21/762 ,  H01L27/088 ,  H01L21/311

    Abstract: A method and structure directed to providing a source/drain isolation structure includes providing a device having a first source/drain region adjacent to a second source/drain region. A masking layer is deposited between the first and second source/drain regions and over an exposed first part of the second source/drain region. After depositing the masking layer, a first portion of an ILD layer disposed on either side of the masking layer is etched, without substantial etching of the masking layer, to expose a second part of the second source/drain region and to expose the first source/drain region. After etching the first portion of the ILD layer, the masking layer is etched to form an L-shaped masking layer. After forming the L-shaped masking layer, a first metal layer is formed over the exposed first source/drain region and a second metal layer is formed over the exposed second part of the second source/drain region.

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