Utrasound probe and ultrasound elasticity imaging apparatus
    61.
    发明申请
    Utrasound probe and ultrasound elasticity imaging apparatus 有权
    超声探头和超声弹性成像仪

    公开(公告)号:US20090018444A1

    公开(公告)日:2009-01-15

    申请号:US12081335

    申请日:2008-04-15

    Abstract: An ultrasound diagnostic apparatus includes an ultrasound probe which transmits/receives an ultrasound wave with respect to a subject to be diagnosed, an ultrasound wave transmit section which transmits an ultrasound wave for driving the ultrasound probe, a pressing section which applies an external pressure to the subject, a displacement measuring section which obtains two tomographic image data different in time series from a reflected echo signal received from the ultrasound probe and measures a displacement of each part in the subject based on the two tomographic image data, an image generating section which generates an elastic image from elasticity information based on the displacement of each part measured by the displacement measuring section, and a display section which displays the generated elastic image. Further, a pressing decision section decides whether or not the pressing operation by the pressing section is proper.

    Abstract translation: 超声波诊断装置包括相对于被诊断对象发送/接收超声波的超声波探头,发送用于驱动超声波探头的超声波的超声波发送部,向外部施加外部压力的按压部, 位移测量部分,其获得与从超声探头接收的反射回波信号不同的时间序列的两个断层图像数据,并且基于两个断层图像数据测量被检体中每个部位的位移;图像生成部,其生成 基于由位移测量部测量的每个部分的位移的弹性信息的弹性图像和显示所生成的弹性图像的显示部。 此外,按压判定部判定按压部的按压操作是否合适。

    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURED THEREOF
    62.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURED THEREOF 有权
    制造半导体器件的方法及其制造的半导体器件

    公开(公告)号:US20080303036A1

    公开(公告)日:2008-12-11

    申请号:US12105318

    申请日:2008-04-18

    CPC classification number: H01L29/66068 H01L29/513 H01L29/7828

    Abstract: Methods of manufacturing a semiconductor device including a semiconductor substrate and a hetero semiconductor region including a semiconductor material having a band gap different from that of the semiconductor substrate and contacting a portion of a first surface of the semiconductor substrate are taught herein, as are the resulting devices. The method comprises depositing a first insulating film on exposed portions of the first surface of the semiconductor substrate and on exposed surfaces of the hetero semiconductor material and forming a second insulating film between the first insulating film and facing surfaces of the semiconductor substrate and the hetero semiconductor region by performing a thermal treatment in an oxidizing atmosphere.

    Abstract translation: 本文教导了制造包括半导体衬底和包括具有与半导体衬底的带隙不同的带隙并与半导体衬底的第一表面的一部分接触的半导体材料的半导体区域的半导体器件的制造方法, 设备。 该方法包括在半导体衬底的第一表面的暴露部分和异质半导体材料的暴露表面上沉积第一绝缘膜,并在第一绝缘膜和半导体衬底和异质半导体的相对表面之间形成第二绝缘膜 通过在氧化气氛中进行热处理。

    Image compression method and image compression device
    64.
    发明授权
    Image compression method and image compression device 有权
    图像压缩方法和图像压缩装置

    公开(公告)号:US07418148B2

    公开(公告)日:2008-08-26

    申请号:US10951757

    申请日:2004-09-27

    Inventor: Tetsuya Hayashi

    Abstract: An image compression device provided for effective utilization of the memory used for image storage and for attaining a reduction in the compression processing time of an image. An image quality evaluation value calculation section calculates the image quality evaluation value of the block for image quality evaluation value calculation which is compressed using four quantization tables in which the quantized data in each is different. A quantization table selection section calculates an approximation curve for approximations or supplies the image quality evaluation value of the block for image quality evaluation value calculation for each quantization table and from the calculated approximation curve further calculates a standard table value for practicable compression to reduce the file size without deterioration of the image quality. Subsequently, a quantization section compresses the original image data using the quantization table with the calculated standard table value.

    Abstract translation: 一种用于有效利用用于图像存储的存储器并且用于减少图像的压缩处理时间的图像压缩装置。 图像质量评估值计算部分计算使用其中每个量化数据不同的四个量化表压缩的图像质量评估值计算块的图像质量评估值。 量化表选择部分计算用于近似的近似曲线或提供用于每个量化表的图像质量评估值计算的块的图像质量评估值,并且从计算出的近似曲线进一步计算用于可实施压缩的标准表值以减少文件 尺寸不会降低图像质量。 随后,量化部分使用具有计算的标准表值的量化表来压缩原始图像数据。

    Electrostatic discharge protection circuit and semiconductor device
    65.
    发明申请
    Electrostatic discharge protection circuit and semiconductor device 有权
    静电放电保护电路和半导体器件

    公开(公告)号:US20080043390A1

    公开(公告)日:2008-02-21

    申请号:US11882865

    申请日:2007-08-06

    CPC classification number: H03K17/08122 H01L27/0251 H03K17/6872

    Abstract: An electrostatic discharge protection circuit and a semiconductor device that prevent the breakdown of a semiconductor device caused by an electrostatic discharge (ESD) which suddenly changes. When voltage which is far higher than VDD1 is applied to a power supply line as a result of an ESD, a great electric potential difference is produced between VDD1 and VSS. At this time an electric current path for making an electric charge generated by overvoltage flow to a grounding line is formed by a clamp circuit. As a result, an electric current flows into GND of a circuit block. This prevents the production of a great electric potential difference between VDD1 and VSS. In addition, at this time a rapid change in the level of the overvoltage applied to a signal line is suppressed by a protection circuit. This prevents the dielectric breakdown of gate oxide films of transistors included in a circuit block which receives a control signal.

    Abstract translation: 一种防止由突然变化的静电放电(ESD)引起的半导体器件击穿的静电放电保护电路和半导体器件。 当远高于VDD 1的电压作为ESD的结果施加到电源线时,在VDD 1和VSS之间产生大的电位差。 此时,通过钳位电路形成用于使由过电压产生的电荷流向接地线的电流路径。 结果,电流流入电路块的GND。 这样可以防止在VDD 1和VSS之间产生很大的电位差。 此外,此时,通过保护电路来抑制施加到信号线的过电压的电平的急剧变化。 这防止包含在接收控制信号的电路块中的晶体管的栅极氧化膜的介电击穿。

    Semiconductor device and manufacturing method thereof
    66.
    发明申请
    Semiconductor device and manufacturing method thereof 有权
    半导体装置及其制造方法

    公开(公告)号:US20070252173A1

    公开(公告)日:2007-11-01

    申请号:US11790791

    申请日:2007-04-27

    Abstract: A semiconductor device is provided with: a semiconductor substrate of a predetermined electroconduction type; a hetero semiconductor region contacted with a first main surface of the semiconductor substrate and comprising a semiconductor material having a bandgap different from that of the semiconductor substrate; a gate electrode formed through a gate insulator layer at a position adjacent to a junction region between the hetero semiconductor region and the semiconductor substrate; a source electrode connected to the hetero semiconductor region; and a drain electrode connected to the semiconductor substrate; wherein the hetero semiconductor region includes a contact portion contacted with the source electrode, at least a partial region of the contact portion is of the same electroconduction type as the electroconduction type of the semiconductor substrate, and the partial region has an impurity concentration higher than an impurity concentration of at least that partial region of a gate-electrode facing portion in the hetero semiconductor region which is positioned to face toward the gate electrode through the gate insulator layer.

    Abstract translation: 半导体器件具有:预定的导电型的半导体衬底; 与所述半导体衬底的第一主表面接触并且包括具有与所述半导体衬底的带隙不同的带隙的半导体材料的异质半导体区域; 在与所述异质半导体区域和所述半导体基板之间的接合区域相邻的位置处形成的栅极电极, 连接到所述异质半导体区的源电极; 和连接到半导体衬底的漏电极; 其中所述异质半导体区域包括与所述源电极接触的接触部分,所述接触部分的至少一部分区域具有与所述半导体衬底的导电型相同的导电类型,并且所述部分区域的杂质浓度高于 至少通过栅极绝缘体层位于面向栅电极的异质半导体区域中的栅电极面对部分的部分区域的杂质浓度。

    Semiconductor device and manufacturing method thereof
    67.
    发明申请
    Semiconductor device and manufacturing method thereof 有权
    半导体器件及其制造方法

    公开(公告)号:US20070252171A1

    公开(公告)日:2007-11-01

    申请号:US11790679

    申请日:2007-04-26

    Abstract: As semiconductor regions in contact with a first main surface of a semiconductor base composed by forming an N− silicon carbide epitaxial layer on an N+ silicon carbide substrate connected to a cathode electrode, there are provided both of an N+ polycrystalline silicon layer of a same conduction type as a conduction type of the semiconductor base and a P+ polycrystalline silicon layer of a conduction type different from the conduction type of the semiconductor base. Both of the N+ polycrystalline silicon layer and the P+ polycrystalline silicon layer are hetero-joined to the semiconductor base, and are ohmically connected to the anode electrode. Moreover, the N+ polycrystalline silicon layer of the same conduction type as the conduction type of the semiconductor base is formed so as to contact the first main surface of the semiconductor base, and the P+ polycrystalline silicon layer of the conduction type different from the conduction type of the semiconductor base is formed in trenches dug on the first main surface of the semiconductor base.

    Abstract translation: 作为与通过在与阴极连接的N +碳化硅衬底上形成N-碳化硅外延层而构成的半导体衬底的第一主表面接触的半导体区域,提供了具有相同导电性的N +多晶硅层 类型为半导体基底的导电类型和不同于半导体基底的导电类型的导电类型的P +多晶硅层。 N +多晶硅层和P +多晶硅层都与半导体基体异相接合,并与欧姆连接到阳极电极。 此外,形成与半导体基底的导电类型相同的导电类型的N +多晶硅层,以便与半导体基底的第一主表面接触,并且与导电类型不同的导电类型的P +多晶硅层 形成在半导体基底的第一主表面上的沟槽中。

    Semiconductor device and manufacturing method thereof
    68.
    发明申请
    Semiconductor device and manufacturing method thereof 有权
    半导体装置及其制造方法

    公开(公告)号:US20070252168A1

    公开(公告)日:2007-11-01

    申请号:US11790792

    申请日:2007-04-27

    Abstract: An electrostatic discharge protection element and a protection resistor, which are formed on an N-drain region with a field oxide film interposed therebetween for the purpose of preventing electrical breakdown of a field effect transistor, are composed as a stacked bidirectional Zener diode of one or a plurality of N+ polycrystalline silicon regions of a first layer and a P+ polycrystalline silicon region of a second layer, and a stacked resistor of one or a plurality of N+ resistor layers of the first layer and an N+ resistor layer of the second layer, respectively. One end of the plurality of N+ polycrystalline silicon regions of the first layer is connected to an external gate electrode terminal, and the other end is connected to a source electrode. One end of the plurality of N+ resistor layers of the first layer is connected to a gate electrode, and the other end is connected to the external gate electrode terminal. Semiconductor regions of the first layer and the second layer are formed by using semiconductor films, which form a hetero semiconductor region and the gate electrode, respectively.

    Abstract translation: 为了防止场效应晶体管的电击穿,形成在其间具有场氧化膜的N-drain区域上的静电放电保护元件和保护电阻器被构成为一个或多个的叠层双向齐纳二极管, 第一层的多个N +多晶硅区域和第二层的P +多晶硅区域,以及第一层的一个或多个N +电阻层和第二层的N +电阻层的层叠电阻器 。 第一层的多个N +多晶硅区域的一端连接到外部栅电极端子,另一端与源电极连接。 第一层的多个N +电阻层的一端连接到栅电极,另一端连接到外部栅电极端子。 通过使用分别形成杂半导体区域和栅电极的半导体膜来形成第一层和第二层的半导体区域。

    Method and apparatus for forming electrode for battery
    69.
    发明申请
    Method and apparatus for forming electrode for battery 失效
    用于形成电池用电极的方法和装置

    公开(公告)号:US20070231464A1

    公开(公告)日:2007-10-04

    申请号:US11706332

    申请日:2007-02-15

    Inventor: Tetsuya Hayashi

    CPC classification number: H01M4/0402 H01M4/1393 H01M10/0525 H01M10/4235

    Abstract: A plurality of gravure rolls are rotated while being allowed to abut against a surface of a moving electrode hoop, thereby applying a coating fluid serving as a precursor of porous layers onto a plurality of linear mixture layers. In this way, a plurality of linear porous layers are formed on the associated linear mixture layers formed on the surface of the electrode hoop. In this case, the location at which each gravure roll abuts against the surface of the electrode hoop is controlled according to variations in the lateral location of associated one of the mixture layers independently of the other gravure rolls.

    Abstract translation: 使多个凹版辊旋转同时抵靠移动电极环的表面,从而将多孔层前体的涂布液施加到多个线性混合物层上。 以这种方式,在形成在电极环的表面上的相关联的线性混合物层上形成多个线性多孔层。 在这种情况下,每个凹版辊邻接电极环的表面的位置根据相关联的一个混合层的侧向位置的变化而独立于其它凹版辊被控制。

    Parking lock releasing apparatus
    70.
    发明申请
    Parking lock releasing apparatus 失效
    停车锁释放装置

    公开(公告)号:US20070209903A1

    公开(公告)日:2007-09-13

    申请号:US11704213

    申请日:2007-02-09

    CPC classification number: B60T7/104 F16H61/22 F16H63/3458 F16H63/3491

    Abstract: A parking lock releasing apparatus includes a manipulator element operable to select a parking range of an automatic transmission, a sensor operable to detect a selection by the manipulator element, an actuator operable to operate a parking lock mechanism of the automatic transmission based on a detection by the sensor, and a manual lever operable to manually release an operation of the parking lock mechanism. The manual lever is operable on condition that a parking brake device is in operation.

    Abstract translation: 一种停车锁释放装置,包括可操作以选择自动变速器的停车范围的操纵器元件,可操作以检测由所述机械手元件进行的选择的传感器,可操作以基于所述自动变速器的检测来操作所述自动变速器的停车锁定机构的致动器 所述传感器和手动操作杆可手动地释放所述停车锁定机构的操作。 在驻车制动装置运行的情况下,手动杆可操作。

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