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178 条记录 (耗时 0.027 秒)

    Substrate mounted connector assembly for interconnecting external circuits and the substrate
    62.
    发明授权
    Substrate mounted connector assembly for interconnecting external circuits and the substrate 失效
    基板安装的连接器组件，用于互连外部电路和基板

    公开(公告)号：US5820390A

    公开(公告)日：1998-10-13

    申请号：US665633

    申请日：1996-06-18

    申请人： Junji Takamoto ,  Takashi Futatsugi ,  Shinichi Hashimoto ,  Ikuo Enomoto

    发明人： Junji Takamoto ,  Takashi Futatsugi ,  Shinichi Hashimoto ,  Ikuo Enomoto

    IPC分类号： H01R13/648 ,  H01R24/00 ,  H01R9/09

    CPC分类号： H01R12/7082 ,  H01R23/6873

    摘要： A first connector 30 mounted on an upper surface of a substrate 10 has a first contact 38 which contacts with a card 32 inserted from one end and extends through a through hole 22 of the substrate 10 at the other end. The first contact 38 is supported by the first connector 30 in a distant position from the substrate 10, and a connecting portion 38c thereof and the through hole 22 are spaced apart. A second connector 60 has a second contact 66 which contacts with an external connector 90 inserted from one end and the connecting portion 38c of the first contact 38 inserted from the other end. The substrate 10, the first and second connectors 30 and 60 are connected each other by connection between the connecting portion 38c and a spring 66c. The first and second connectors 30 and 60 include shield shells 40 and 68 covering the first and second connectors 30 and 60, respectively, and the shield shells 40 and 68 are maintained in the same electric potential through a ground electrode of the substrate 10 to effectively prevent unwanted emission caused by a ground potential difference between connectors.

    摘要翻译： 安装在基板10的上表面上的第一连接器30具有与从一端插入的卡32接触并且在另一端延伸穿过基板10的通孔22的第一触点38。 第一触点38由第一连接器30支撑在与基板10相距较远的位置，并且其连接部分38c和通孔22间隔开。 第二连接器60具有与从一端插入的外部连接器90和从另一端插入的第一触头38的连接部分38c接触的第二触点66。 基板10，第一和第二连接器30和60通过连接部分38c和弹簧66c之间的连接彼此连接。 第一和第二连接器30和60分别包括覆盖第一和第二连接器30和60的屏蔽壳40和68，并且屏蔽壳40和68通过基板10的接地电极保持在相同的电位，以有效地 防止由连接器之间的接地电位差引起的不必要的发射。

    Delay correction circuit for semiconductor tester
    63.
    发明授权
    Delay correction circuit for semiconductor tester 失效
    半导体测试仪的延迟校正电路

    公开(公告)号：US5796749A

    公开(公告)日：1998-08-18

    申请号：US776835

    申请日：1997-04-25

    申请人： Shinichi Hashimoto

    发明人： Shinichi Hashimoto

    IPC分类号： G01R31/28 ,  G01R31/319 ,  H03K5/135 ,  G06F11/00

    CPC分类号： G01R31/3191

    摘要： The present invention is to provide a delay correction circuit for a semiconductor tester which can decrease a circuit size and electric power consumption in a timing correction part. To achieve this goal, a variable delay element which corrects the phase difference stemming from the common parts of test stations is provided at an output of a waveform controller. At an output of a waveform output controller which generates the signal determining whether a signal should be applied to the test stations, flip-flops are provided which perform an inter-leave function. A gate circuit is provided which combines each unit of the inter-leave function based on the output signal of the variable delay element. An AND gate is provided which takes the logical AND between the output of the gate circuit corresponding to the test station and the output of the variable delay element. A variable delay element which corrects the phase difference stemming from each test station is provided at the output of the AND gate.

    摘要翻译： PCT No.PCT / JP95 / 01733 Sec。 371日期1997年04月25日 102（e）日期1997年4月25日PCT提交1995年8月31日PCT公布。 公开号WO97 / 08563 日期：1997年3月6日本发明提供一种能够降低定时校正部分的电路尺寸和电力消耗的半导体测试器的延迟校正电路。 为了实现这一目标，在波形控制器的输出处提供校正来自测试站的公共部分的相位差的可变延迟元件。 在产生确定是否应将信号施加到测试台的信号的波形输出控制器的输出处，提供执行间歇功能的触发器。 提供了一种门电路，其基于可变延迟元件的输出信号组合了间歇功能的每个单元。 提供了与门，其将与测试站对应的门电路的输出与可变延迟元件的输出之间的逻辑“和”。 在AND门的输出处提供校正来自每个测试台的相位差的可变延迟元件。

    Surface mount connector
    65.
    发明授权
    Surface mount connector 失效
    表面贴装连接器

    公开(公告)号：US5727957A

    公开(公告)日：1998-03-17

    申请号：US780766

    申请日：1997-01-08

    申请人： Shinichi Hashimoto ,  Yoshitsugu Fujiura

    发明人： Shinichi Hashimoto ,  Yoshitsugu Fujiura

    IPC分类号： H01R12/71 ,  H01R13/26 ,  H01R13/40 ,  H01R43/16 ,  H01R9/09

    CPC分类号： H01R12/57 ,  H01R12/725 ,  H01R13/26 ,  H01R43/16

    摘要： An electrical connector 10 has electrical contacts 30a, 30b arranged in cavities 40a, 40b of a housing 50. Electrical contacts 30a, 30b include contact sections 31 and termination sections 32a, 32b having plate sections 36 oriented perpendicular to a surface of the contact sections 31 and soldering termination members 37. When electrical contacts 30a, 30b are placed in the housing 50, a rear portion 34 of the contact section 31 can be bent due to the fact that cut-outs 47a, 47b corresponding to the rear portion 34 are provided in the inside walls of cavities 40a, 40b, thus allowing for elastic deformation of the rear portion 34. In addition, plate sections 36 have lugs 38 accommodated in grooves 55 formed in the housing 50. Because of resilience of the rear sections 34, the lugs 38 engage against bottom surfaces 56 of the grooves 55, thus determining the position of the soldering termination members 37.

    摘要翻译： 电连接器10具有布置在壳体50的空腔40a，40b中的电触头30a，30b。电触点30a，30b包括接触部分31和端接部分32a，32b，其具有垂直于接触部分31的表面定向的板部分36 以及焊接端子构件37.当将电触头30a，30b放置在壳体50中时，由于与后部34对应的切口47a，47b设置在接触部31的后部34上，所以可以弯曲接触部31的后部34 在空腔40a，40b的内壁中，从而允许后部34的弹性变形。此外，板部36具有容纳在形成于壳体50中的槽55中的凸耳38.由于后部34的弹性， 凸耳38接合凹槽55的底表面56，从而确定焊接端接构件37的位置。

    Method of separating a semiconductor wafer with dielectrics
    66.
    发明授权
    Method of separating a semiconductor wafer with dielectrics 失效
    用电介质分离半导体晶片的方法

    公开(公告)号：US5607875A

    公开(公告)日：1997-03-04

    申请号：US454918

    申请日：1995-05-31

    申请人： Masato Nishizawa ,  Shinichi Hashimoto ,  Yoshiyuki Sugahara

    发明人： Masato Nishizawa ,  Shinichi Hashimoto ,  Yoshiyuki Sugahara

    IPC分类号： H01L21/02 ,  H01L21/76 ,  H01L21/762 ,  H01L21/763 ,  H01L27/12

    CPC分类号： H01L21/763 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/76286 ,  Y10S148/05

    摘要： A method for separating a joined substrate type wafer, which wafer is composed of a pair of semiconductor substrates joined through an insulation film, utilizes dielectrics through simple processing steps. Trenches for separating a semiconductor substrate with dielectrics are dug from the surface of the substrate and a dielectrics film is deposited on the surface of the substrate including the trenches. Then poly-crystalline silicon is grown by CVD to a thickness of about 0.5 .mu.m, which is deep enough to fill the trenches. The process time for growing poly-crystalline silicon is shortened, and the processing step for removing the poly-crystalline silicon deposited on the unwanted areas is eliminated by growing the poly-crystalline silicon in the trenches but not on the crystalline surface of semiconductor regions based on the growth rate dependence of the poly-crystalline silicon on the crystallinity of the surface on which the poly-crystalline silicon is grown.

    摘要翻译： 用于分离由通过绝缘膜连接的一对半导体基板构成的晶片的接合基板型晶片的方法通过简单的处理步骤来利用电介质。 用于从电介质表面分离半导体衬底的沟槽从衬底的表面被挖出，并且在包括沟槽的衬底的表面上沉积电介质膜。 然后通过CVD将多晶硅生长至约0.5μm的厚度，其足够深以填充沟槽。 缩短生长多晶硅的处理时间，并且通过在沟槽中生长多晶硅而不是在半导体区域的晶体表面上生长多晶硅以消除沉积在不想要的区域上的多晶硅的处理步骤 关于多晶硅对生长多晶硅的表面的结晶度的生长速率依赖性。

    Method for the manufacture of silver halide photographic materials
    67.
    发明授权
    Method for the manufacture of silver halide photographic materials 失效
    制造卤化银照相材料的方法

    公开(公告)号：US5096803A

    公开(公告)日：1992-03-17

    申请号：US510774

    申请日：1990-04-18

    申请人： Satoshi Kanetake ,  Shinichi Hashimoto

    发明人： Satoshi Kanetake ,  Shinichi Hashimoto

    IPC分类号： G03C1/74 ,  G03C1/795

    CPC分类号： G03C1/74 ,  G03C1/7954 ,  G03C2001/7451 ,  Y10S430/136 ,  Y10S430/14

    摘要： A method for producing a silver halide photographic material which comprises the steps of:(a) coating hydrophilic colloid coating liquid on a polyester support;(b) forming a hydrophilic colloid layer by drying said hydrophilic coating liquid, when A is not more than 300, in an atmosphere having a relative humidity of not more than 50% and such that the ratio A/B is at least 18whereinA is determined by the following formula:A=(M/S).times.100 wherein M represents the moisture content by weight of said hydrophilic colloid layer on said support and S represents the solid weight of said hydrophilic colloid layer on said support, andB is the drying time until A is not more than 8 expressed in seconds; and(C) heat treating said coated supported from step (b) at a temperature of at least 30.degree. C. in a atmosphere having an absolute humidity of not more than 1%.The method of the present invention provides silver halide photographic materials which have improved dimensional stability.

    摘要翻译： 一种卤化银照相材料的制造方法，其特征在于，包括以下步骤：（a）将亲水胶体涂布液涂布在聚酯载体上; （b）在相对湿度不大于50％且A / B比至少为18的气氛中，当A不大于300时，通过干燥所述亲水性涂布液形成亲水胶体层，其中A 由下式确定：A =（M / S）×100其中M表示所述载体上所述亲水胶体层的水分含量，S表示所述载体上所述亲水胶体层的固体重量，B为 干燥时间直到A不超过8表示秒; 和（C）在绝对湿度不超过1％的气氛中，在至少30℃的温度下，对步骤（b）负载的所述涂层进行热处理。 本发明的方法提供了具有改进的尺寸稳定性的卤化银照相材料。