公开(公告)号：US20170194352A1

公开(公告)日：2017-07-06

申请号：US15464426

申请日：2017-03-21

Applicant: Texas Instruments Incorporated

Inventor： Alexei Sadovnikov ,  Jeffrey A. Babcock

IPC: H01L27/12 ,  H01L23/535 ,  H01L27/082 ,  H01L29/10 ,  H01L29/735 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L27/1203 ,  H01L23/535 ,  H01L27/082 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/10 ,  H01L29/1008 ,  H01L29/66265 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/735

Abstract: Complementary high-voltage bipolar transistors in silicon-on-insulator (SOl) integrated circuits is disclosed. In one disclosed embodiment, a collector region is formed in an epitaxial silicon layer disposed over a buried insulator layer. A base region and an emitter are disposed over the collector region. An n-type region is formed under the buried insulator layer (BOX) by implanting donor impurity through the active region of substrate and BOX into a p-substrate. Later in the process flow this n-type region is connected from the top by doped poly-silicon plug and is biased at Vcc. In this case it will deplete lateral portion of PNP collector region and hence, will increase its BV.

公开(公告)号：US20170125252A1

公开(公告)日：2017-05-04

申请号：US14930633

申请日：2015-11-02

Applicant: Texas Instruments Incorporated

Inventor： Andrew D. Strachan ,  Alexei Sadovnikov ,  Christopher Boguslaw Kocon

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/10 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L21/28114 ,  H01L21/28158 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42356 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7831 ,  H01L29/7835

Abstract: A semiconductor device includes a split-gate lateral extended drain MOS transistor, which includes a first gate and a second gate laterally adjacent to the first gate. The first gate is laterally separated from the second gate by a gap of 10 nanometers to 250 nanometers. The first gate extends at least partially over the body, and the second gate extends at least partially over a drain drift region. The drain drift region abuts the body at a top surface of the substrate. A boundary between the drain drift region and the body at the top surface of the substrate is located under at least one of the first gate, the second gate and the gap between the first gate and the second gate. The second gate may be coupled to a gate bias voltage node or a gate signal node.

公开(公告)号：US09633995B2

公开(公告)日：2017-04-25

申请号：US15050808

申请日：2016-02-23

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey A. Babcock ,  Alexei Sadovnikov

IPC: H01L21/8249 ,  H01L27/06 ,  H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L29/423 ,  H01L21/3213 ,  H01L29/06 ,  H01L29/45 ,  H01L29/49

CPC classification number: H01L27/0623 ,  H01L21/32139 ,  H01L21/8249 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/402 ,  H01L29/423 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66553 ,  H01L29/66575 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/66712 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7824 ,  H01L29/7835

Abstract: A method of fabricating a MOSFET transistor in a SiGe BICMOS technology and resulting structure having a drain-gate feedback capacitance shield formed between a gate electrode and the drain region. The shield does not overlap the gate and thereby minimizes effect on the input capacitance of the transistor. The process does not require complex or costly processing since the shield is composed of bipolar base material commonly used in SiGe BICMOS technologies.

公开(公告)号：US20160172355A1

公开(公告)日：2016-06-16

申请号：US15050684

申请日：2016-02-23

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey A. Babcock ,  Alexei Sadovnikov

IPC: H01L27/06 ,  H01L29/40 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/0623 ,  H01L21/32139 ,  H01L21/8249 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/402 ,  H01L29/423 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66553 ,  H01L29/66575 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/66712 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7824 ,  H01L29/7835

Abstract: A method of fabricating a MOSFET transistor in a SiGe BICMOS technology and resulting structure having a drain-gate feedback capacitance shield formed between a gate electrode and the drain region. The shield does not overlap the gate and thereby minimizes effect on the input capacitance of the transistor. The process does not require complex or costly processing since the shield is composed of bipolar base material commonly used in SiGe BICMOS technologies.

Abstract translation: 一种以SiGe BICMOS技术制造MOSFET晶体管的方法，其结构在栅电极和漏极区之间形成漏极 - 栅极反馈电容屏蔽。 屏蔽不与栅极重叠，从而最小化对晶体管的输入电容的影响。 该过程不需要复杂或昂贵的处理，因为屏蔽由SiGe BICMOS技术中通常使用的双极母材组成。

公开(公告)号：US09343459B2

公开(公告)日：2016-05-17

申请号：US14245099

申请日：2014-04-04

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey A. Babcock ,  Alexei Sadovnikov

IPC: H01L21/8238 ,  H01L27/082 ,  H01L29/06 ,  H01L29/04 ,  H01L29/16 ,  H01L21/265 ,  H01L21/266 ,  H01L21/762 ,  H01L21/306 ,  H01L21/308 ,  H01L29/08 ,  H01L21/8228

CPC classification number: H01L29/063 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/8228 ,  H01L21/82285 ,  H01L27/082 ,  H01L27/0826 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/732

Abstract: Complementary high-voltage bipolar transistors formed in standard bulk silicon integrated circuits are disclosed. In one disclosed embodiment, collector regions are formed in an epitaxial silicon layer. Base regions and emitters are disposed over the collector region. An n-type region is formed under collector region by implanting donor impurities into a p-substrate for the PNP transistor and implanting acceptor impurities into the p-substrate for the NPN transistor prior to depositing the collector epitaxial regions. Later in the process flow these n-type and p-type regions are connected to the top of the die by a deep n+ and p+ wells respectively. The n-type well is then coupled to VCC while the p-type well is coupled to GND, providing laterally depleted portions of the PNP and NPN collector regions and hence, increasing their BVs.

Abstract translation: 公开了在标准体硅集成电路中形成的互补高电压双极晶体管。 在一个公开的实施例中，集电极区域形成在外延硅层中。 基极区域和发射极设置在集电极区域上。 通过将供体杂质注入用于PNP晶体管的p衬底中并在沉积集电极外延区之前将受体杂质注入到NPN晶体管的p衬底中，在集电极区域形成n型区域。 在工艺流程中，这些n型和p型区域分别通过深n +和p +阱连接到管芯的顶部。 然后将n型阱耦合到VCC，而p型阱耦合到GND，提供PNP和NPN集电极区域的横向耗尽部分，并因此增加其BV。

公开(公告)号：US20150270335A1

公开(公告)日：2015-09-24

申请号：US14219760

申请日：2014-03-19

Applicant: Texas Instruments Incorporated

Inventor： Alexei Sadovnikov ,  Jeffrey A. Babcock

IPC: H01L29/06 ,  H01L27/082 ,  H01L29/45 ,  H01L27/12 ,  H01L29/08

CPC classification number: H01L27/1203 ,  H01L23/535 ,  H01L27/082 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/10 ,  H01L29/1008 ,  H01L29/66265 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/735

Abstract: Complementary high-voltage bipolar transistors in silicon-on-insulator (SOI) integrated circuits is disclosed. In one disclosed embodiment, a collector region is formed in an epitaxial silicon layer disposed over a buried insulator layer. A base region and an emitter are disposed over the collector region. An n-type region is formed under the buried insulator layer (BOX) by implanting donor impurity through the active region of substrate and BOX into a p-substrate. Later in the process flow this n-type region is connected from the top by doped poly-silicon plug and is biased at Vcc. In this case it will deplete lateral portion of PNP collector region and hence, will increase its BV.

Abstract translation: 公开了绝缘体上硅（SOI）集成电路中的互补高压双极晶体管。 在一个公开的实施例中，集电极区域形成在设置在掩埋绝缘体层上的外延硅层中。 基极区域和发射极设置在集电极区域上方。 通过将施主杂质通过衬底和BOX的有源区注入到p衬底中，在掩埋绝缘体层（BOX）下方形成n型区域。 在该过程流程中，该n型区域从顶部通过掺杂的多晶硅插头连接并且被偏置在Vcc。 在这种情况下，它将消耗PNP集电极区域的侧面部分，因此将增加其BV。

公开(公告)号：US12243939B2

公开(公告)日：2025-03-04

申请号：US17515531

申请日：2021-10-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Gang Xue ,  Pushpa Mahalingam ,  Alexei Sadovnikov

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66

Abstract: Described examples include an integrated circuit having a transistor with a first gate on a first gate insulating layer. The transistor also has second gate separated from the first gate by a gate gap. The integrated circuit also includes a channel well at the gate gap extending under the first gate and the second gate. The transistor has a first source in the channel adjacent to an edge of the first gate. The transistor having a second source formed in the channel adjacent to an edge of the second gate separated from the first source by a channel gap. The transistor has at least one back-gate contact, the at least one back-gate contact separated from the first gate by a first back-gate contact gap and separated from the second gate by a second back-gate contact gap.

公开(公告)号：US20240222527A1

公开(公告)日：2024-07-04

申请号：US18147875

申请日：2022-12-29

Applicant: Texas Instruments Incorporated

Inventor： Alexei Sadovnikov ,  Natalia Lavrovskaya ,  Archana Venugopal

IPC: H01L29/866 ,  H01L29/06 ,  H01L29/36 ,  H01L29/66

CPC classification number: H01L29/866 ,  H01L29/0646 ,  H01L29/36 ,  H01L29/66106

Abstract: Breakdown diodes and methods of making the same are described. Such a breakdown diode can be fabricated in a semiconductor substrate and have a junction configured to breakdown under a target reverse bias applied across the junctions. The junction is located below the surface of the substrate by a distance suitable for ameliorating mechanical stress impact to the reverse bias breakdown voltage of the junction. Moreover, the junction is located away from an interface causing noise issues.

公开(公告)号：US12015054B2

公开(公告)日：2024-06-18

申请号：US17710320

申请日：2022-03-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Alexei Sadovnikov ,  Guruvayurappan S. Mathur

IPC: H01L29/06 ,  H01L21/265 ,  H01L21/761 ,  H01L29/66 ,  H01L29/73

CPC classification number: H01L29/0619 ,  H01L21/26513 ,  H01L21/761 ,  H01L29/66234 ,  H01L29/73

Abstract: A method includes implanting dopant of a first conductivity type into an epitaxial layer of semiconductor material to form first and second false collector regions adjacent to the surface of the epitaxial layer. The first false collector region is located laterally on a first side of a base region. The base region is formed within the epitaxial layer from dopant of a second conductivity type that is opposite the first conductivity type. The second false collector region is located laterally on a second side of the base region. The second side is opposite the first side of the base region. The base region is a base of a parasitic bipolar junction in an isolation region of an active semiconductor device.

公开(公告)号：US20230343828A1

公开(公告)日：2023-10-26

申请号：US17727892

申请日：2022-04-25

Applicant: Texas Instruments Incorporated

Inventor： Alexei Sadovnikov ,  Ming-Yeh Chuang ,  Jingjing Chen

IPC: H01L29/10 ,  H01L29/78 ,  H01L21/265 ,  H01L21/266 ,  H01L21/74 ,  H01L29/66

CPC classification number: H01L29/1083 ,  H01L29/7816 ,  H01L29/1095 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/74 ,  H01L29/66681

Abstract: A method of fabricating a transistor includes forming a gate structure over a semiconductor substrate having a first conductivity type. A photoresist layer is patterned over the gate structure to remove the photoresist layer from over an uncovered portion of the gate structure and an adjacent region of the semiconductor substrate abutting the uncovered portion of the gate structure. A deep well region having the first conductivity type is formed using a first dopant such that the first dopant penetrates through the uncovered portion of the gate structure and is blocked by the photoresist layer. A shallow well region is formed by implanting a second dopant such that the second dopant penetrates the adjacent region and is blocked by the uncovered portion of the gate structure.