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    LATERALLY DIFUSED METAL-OXIDE SEMICONDUCTOR (LDMOS) TRANSISTOR WITH INTEGRATED BACK-GATE
    2.
    发明申请
    LATERALLY DIFUSED METAL-OXIDE SEMICONDUCTOR (LDMOS) TRANSISTOR WITH INTEGRATED BACK-GATE 有权

    公开(公告)号：US20230136827A1

    公开(公告)日：2023-05-04

    申请号：US17515531

    申请日：2021-10-31

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Gang Xue ,  Pushpa Mahalingam ,  Alexei Sadovnikov

    IPC: H01L29/78 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66

    Abstract: Described examples include an integrated circuit having a transistor with a first gate on a first gate insulating layer. The transistor also has second gate separated from the first gate by a gate gap. The integrated circuit also includes a channel well at the gate gap extending under the first gate and the second gate. The transistor has a first source in the channel adjacent to an edge of the first gate. The transistor having a second source formed in the channel adjacent to an edge of the second gate separated from the first source by a channel gap. The transistor has at least one back-gate contact, the at least one back-gate contact separated from the first gate by a first back-gate contact gap and separated from the second gate by a second back-gate contact gap.

    Laterally diffused metal-oxide semiconductor (LDMOS) transistor with integrated back-gate
    4.
    发明授权
    Laterally diffused metal-oxide semiconductor (LDMOS) transistor with integrated back-gate 有权

    公开(公告)号：US12243939B2

    公开(公告)日：2025-03-04

    申请号：US17515531

    申请日：2021-10-31

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Gang Xue ,  Pushpa Mahalingam ,  Alexei Sadovnikov

    IPC: H01L29/78 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66

    Abstract: Described examples include an integrated circuit having a transistor with a first gate on a first gate insulating layer. The transistor also has second gate separated from the first gate by a gate gap. The integrated circuit also includes a channel well at the gate gap extending under the first gate and the second gate. The transistor has a first source in the channel adjacent to an edge of the first gate. The transistor having a second source formed in the channel adjacent to an edge of the second gate separated from the first source by a channel gap. The transistor has at least one back-gate contact, the at least one back-gate contact separated from the first gate by a first back-gate contact gap and separated from the second gate by a second back-gate contact gap.

    RUGGED LDMOS WITH DRAIN-TIED FIELD PLATE
    5.
    发明申请
    RUGGED LDMOS WITH DRAIN-TIED FIELD PLATE 有权

    公开(公告)号：US20220149186A1

    公开(公告)日：2022-05-12

    申请号：US17092485

    申请日：2020-11-09

    Applicant: Texas Instruments Incorporated

    Inventor： Henry Litzmann Edwards ,  Gang Xue

    IPC: H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/08 ,  H01L21/762

    Abstract: A semiconductor device including a substrate having a semiconductor layer containing a laterally diffused metal oxide semiconductor (LDMOS) transistor, including a body region of a first conductivity type and a drift region of an opposite conductivity type. A gate dielectric layer over a channel region of the body, the gate dielectric extending over a junction between a body region and the drift region with a gate electrode on the gate dielectric and a drain contact in the drain drift region, having the second conductivity type. A field relief dielectric layer on the drain drift region extending from the drain region to the gate dielectric, having a thickness greater than the gate dielectric layer. A drain-tied field plate on the field relief dielectric, the drain-tied field plate extending from the drain region toward the gate with an electrical connection between the drain-tied field plate and the drain region.

    Low dynamic resistance low capacitance diodes
    6.
    发明授权
    Low dynamic resistance low capacitance diodes 有权

    公开(公告)号：US10153269B2

    公开(公告)日：2018-12-11

    申请号：US15679592

    申请日：2017-08-17

    Applicant: Texas Instruments Incorporated

    Inventor： Andrew D. Strachan ,  Alexei Sadovnikov ,  Gang Xue ,  Dening Wang

    IPC: H01L27/02 ,  H01L29/06 ,  H01L29/861 ,  H01L29/66

    Abstract: A low dynamic resistance, low capacitance diode of a semiconductor device includes a heavily-doped n-type substrate. A lightly-doped n-type layer 1 micron to 5 microns thick is disposed on the n-type substrate. A lightly-doped p-type layer 3 microns to 8 microns thick is disposed on the n-type layer. The low dynamic resistance, low capacitance diode, of the semiconductor device includes a p-type buried layer, with a peak dopant density above 1×1017 cm−3, extending from the p-type layer through the n-type layer to the n-type substrate. The low dynamic resistance, low capacitance diode also includes an n-type region disposed in the p-type layer, extending to a top surface of the p-type layer.

    ELECTROSTATIC DISCHARGE PROTECTION DEVICES WITH LOW CAPACITANCE
    8.
    发明申请
    ELECTROSTATIC DISCHARGE PROTECTION DEVICES WITH LOW CAPACITANCE 有权

    公开(公告)号：US20250126879A1

    公开(公告)日：2025-04-17

    申请号：US18484655

    申请日：2023-10-11

    Applicant: Texas Instruments Incorporated

    Inventor： Kartikey Mayurkumar Thakar ,  Sunglyong Kim ,  Gang Xue ,  Tian Ping Lv

    IPC: H01L27/08 ,  H01L21/8222

    Abstract: Diodes for ESD protection devices are described. The diodes have low capacitance. In an example, a semiconductor device includes a substrate, an n-type epitaxial layer on the n-type substrate in a first region of the n-type substrate, and a p-type epitaxial layer on the n-type epitaxial layer with an interface between the n-type and p-type epitaxial layers. The p-type epitaxial layer has a first concentration of p-type dopants throughout the p-type epitaxial layer. Also, the semiconductor device includes a p-type dopant distribution straddling across the interface, the p-type dopant distribution having a first peak concentration of p-type dopants greater than the first concentration, and an n-type dopant distribution straddling across the interface, the n-type dopant distribution having a second peak concentration of n-type dopants. The second peak concentration is substantially same as the first peak concentration.

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