公开(公告)号：US20230335555A1

公开(公告)日：2023-10-19

申请号：US17720944

申请日：2022-04-14

Applicant: TOKYO ELECTRON LIMITED

Inventor： Mark I. GARDNER ,  Robert D. CLARK ,  H. Jim FULFORD

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/786 ,  H01L29/78 ,  H01L29/51

CPC classification number: H01L27/0922 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/823885 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78648

Abstract: A semiconductor device includes a substrate having a substrate surface, a transistor stack provided on the substrate surface and including a plurality of transistors stacked on each other along a vertical direction that is perpendicular to the substrate surface. Each transistor in the transistor stack includes a vertical channel structure extending along the vertical direction and having a first vertical sidewall and a second vertical sidewall opposite to the first vertical sidewall, and a ferroelectric gate structure in contact with the first vertical sidewall of the vertical channel structure; and a back gate structure provided on the substrate and in contact with the second vertical sidewall of the vertical channel structure of each respective transistor in the transistor stack.

公开(公告)号：US20230320069A1

公开(公告)日：2023-10-05

申请号：US17989348

申请日：2022-11-17

Applicant: Tokyo Electron Limited

Inventor： H. Jim FULFORD ,  Mark I. GARDNER ,  Partha MUKHOPADHYAY

IPC: H01L27/108

CPC classification number: H01L27/10805 ,  H01L27/1085 ,  H01L27/10873

Abstract: Aspects of the present disclosure provide a semiconductor structure, which can include a lower transistor including a lower channel that is elongated horizontally and includes a lower doped first-type semiconductor layer of a lower doped semiconductor layer, an upper transistor vertically stacked over the lower transistor and including an upper channel that is elongated horizontally and includes an upper doped first-type semiconductor layer of an upper doped semiconductor layer, a lower capacitor electrically connected to and horizontally elongated from the lower transistor and including a first lower plate that includes a lower doped second-type semiconductor layer of the lower doped semiconductor layer, and an upper capacitor vertically stacked over the lower capacitor and electrically connected to and horizontally elongated from the upper transistor and including a first upper plate that includes an upper doped second-type semiconductor layer of the upper doped semiconductor layer.

公开(公告)号：US20230301061A1

公开(公告)日：2023-09-21

申请号：US18073118

申请日：2022-12-01

Applicant: Tokyo Electron Limited

Inventor： H. Jim FULFORD ,  Mark I. GARDNER ,  Partha MUKHOPADHYAY

IPC: H10B12/00 ,  H01L29/423 ,  H01L29/786 ,  H01L29/778

CPC classification number: H01L27/10805 ,  H01L27/1085 ,  H01L27/10873 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/7869 ,  H01L29/778

Abstract: A semiconductor device includes a stack of dynamic random access memory (DRAM) cell units over a substrate in a vertical direction perpendicular to a working surface of the substrate. At least one DRAM cell unit includes a transistor and a capacitor. The capacitor includes a first metal layer, a capacitor dielectric layer positioned on the first metal layer, and a second metal layer positioned on the capacitor dielectric layer. The capacitor is elongated in a horizontal direction parallel to the working surface of the substrate. The second metal layer has a first end and a second end in the horizontal direction. The transistor includes a channel structure, and a gate structure disposed all around the channel structure. The first metal layer extends in the horizontal direction beyond the first end of the second metal layer to form a drain region and a source region of the transistor.

公开(公告)号：US20230251574A1

公开(公告)日：2023-08-10

申请号：US17890766

申请日：2022-08-18

Applicant: Tokyo Electron Limited

Inventor： Anthony R. SCHEPIS ,  Daniel J. FULFORD ,  Mark I. GARDNER ,  H. Jim FULFORD ,  Anton J. DEVILLIERS

IPC: G03F7/11 ,  G01B11/16 ,  G03F7/20

CPC classification number: G03F7/11 ,  G01B11/16 ,  G03F7/70783 ,  G03F7/70483

Abstract: Aspects of the present disclosure provide a method for optimizing wafer shape. For example, the method can include receiving a wafer having a working surface for one or more devices to be fabricated thereon and a backside surface opposite to the working surface, measuring the wafer to identify bow measurement of the wafer, and forming a first stress-modification film on the backside surface. The first stress-modification film can be reactive to a first wavelength of light in that exposure to the first wavelength of light modifies an internal stress of the first stress-modification film. The method can further include exposing the first stress-modification film to a pattern of the first wavelength of light to modify the internal stress of the first stress-modification film. The pattern of the first wavelength of light corresponds to the bow measurement.

公开(公告)号：US20230245929A1

公开(公告)日：2023-08-03

申请号：US17592032

申请日：2022-02-03

Applicant: Tokyo Electron Limited

Inventor： H. Jim FULFORD ,  Mark I. GARDNER

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L21/823487 ,  H01L27/088 ,  H01L29/7827

Abstract: Aspects of the present disclosure provide 3D semiconductor structures and methods for fabricating the same. For example, the method can include forming a first multilayer stack over a substrate, forming a second multilayer stack over the first multilayer stack, forming a first opening through the first and second multilayer stack until uncovering a top surface of the substrate, forming in the first opening a first vertical field-effect transistor (VFET) over the substrate, and forming in the first opening a second VFET over the first VFET. The first VFET can include a first channel having a first length corresponding to a first thickness of a first layer of the first multilayer stack. The second VFET can include a second channel having a second length corresponding to a second thickness of a second layer of the second multilayer stack. The second thickness can be different from the first thickness.

公开(公告)号：US20230207667A1

公开(公告)日：2023-06-29

申请号：US17952552

申请日：2022-09-26

Applicant: Tokyo Electron Limited

Inventor： H. Jim FULFORD ,  Mark I. GARDNER ,  Partha MUKHOPADHYAY

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L23/528 ,  H01L29/786

CPC classification number: H01L29/66795 ,  H01L29/0665 ,  H01L29/4236 ,  H01L29/41725 ,  H01L23/528 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate, a first wiring layer over the substrate, and a first array of transistor pairs extending over the first wiring layer. Cross sections of each transistor pair cut through the first array. The cross sections of each transistor pair have a similar structure. Each transistor pair includes a mandrel having two opposite sidewalls that are perpendicular to the substrate and extending along a direction of the first array of transistor pairs. Each transistor pair includes two transistors symmetrically disposed over the two opposite sidewalls of the respective mandrel.

公开(公告)号：US20230187280A1

公开(公告)日：2023-06-15

申请号：US17546755

申请日：2021-12-09

Applicant: Tokyo Electron Limited

Inventor： Mark I. GARDNER ,  H. Jim FULFORD

IPC: H01L21/822 ,  H01L27/06 ,  H01L27/11556 ,  H01L27/11568 ,  H01L29/786

CPC classification number: H01L21/8221 ,  H01L27/0688 ,  H01L27/11556 ,  H01L27/11568 ,  H01L29/78696

Abstract: A semiconductor device includes a stack of layers defining a sidewall surface and comprising source and drain layers. A channel structure extends through the stack of layers, is oriented in a vertical direction perpendicular to a main surface of the stack of layers, and is configured to have a current flow path in the vertical direction. The channel structure includes a two-dimensional (2D) semiconductor material. A core structure is positioned inside and surrounded by the channel structure, and a gate structure surrounds at least part of the channel structure.

公开(公告)号：US20230163185A1

公开(公告)日：2023-05-25

申请号：US17714716

申请日：2022-04-06

Applicant: Tokyo Electron Limited

Inventor： H. Jim FULFORD ,  Mark I. GARDNER ,  Partha MUKHOPADHYAY

IPC: H01L29/423 ,  H01L27/06 ,  H01L29/786 ,  H01L29/06 ,  H01L29/417 ,  H01L21/822

CPC classification number: H01L29/42392 ,  H01L27/0688 ,  H01L29/78696 ,  H01L29/0665 ,  H01L29/41775 ,  H01L21/8221

Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor includes a first channel structure positioned over a substrate, first source/drain (S/D) regions positioned on ends of the first channel structure, and a first gate structure disposed all around the first channel structure. The second transistor includes a second channel structure positioned over the first channel structure, second S/D regions positioned on ends of the second channel structure, and a second gate structure disposed all around the second channel structure. The second channel structure has a smaller dimension than the first channel structure in a horizontal direction substantially parallel to a working surface of the substrate.

公开(公告)号：US20230056372A1

公开(公告)日：2023-02-23

申请号：US17714678

申请日：2022-04-06

Applicant: Tokyo Electron Limited

Inventor： Mark I. GARDNER ,  H. Jim FULFORD ,  Partha MUKHOPADHYAY

IPC: H01L29/423 ,  H01L27/06 ,  H01L21/822 ,  H01L29/786 ,  H01L29/06 ,  H01L29/417

Abstract: A method of microfabrication includes forming an initial stack of semiconductor layers by epitaxial growth over a substrate. The initial stack of semiconductor layers is surrounded by a sidewall structure. The initial stack of semiconductor layers includes channel structures and sacrificial gate layers stacked alternatingly in a vertical direction substantially perpendicular to a working surface of the substrate. The channel structures include a first channel structure and a second channel structure positioned above the first channel structure. First portions of the sidewall structure are removed to uncover first sides of the initial stack. Source/drain (S/D) regions are formed on uncovered side surfaces of the channel structures from the first sides of the initial stack. Second portions of the sidewall structure are removed to uncover second sides of the initial stack. The sacrificial gate layers are replaced with gate structures from the second sides of the initial stack.

公开(公告)号：US20220254690A1

公开(公告)日：2022-08-11

申请号：US17480336

申请日：2021-09-21

Applicant: Tokyo Electron Limited

Inventor： H. Jim FULFORD ,  Mark I. GARDNER

IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/423

Abstract: A method of microfabrication is provided. The method includes forming shell structures above a first layer including a first semiconductor material. The shell structures are electrically isolated from each other and electrically isolated from the first layer. The shell structures include at least one type of semiconductor material and each include a dielectric core structure. Each shell structure is configured to include a top source/drain (S/D) region, a channel region and a bottom S/D region serially connected in a vertical direction perpendicular to the first layer and have a current flow path in the vertical direction. A bottom contact structure connected to a respective bottom S/D region of each shell structure is formed. A gate structure is formed on a sidewall of a respective channel region of each shell structure.