公开(公告)号：US20240413015A1

公开(公告)日：2024-12-12

申请号：US18220803

申请日：2023-07-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kuang Hsieh ,  Chien-Ting Lin ,  Ssu-I Fu ,  Chin-Hung Chen

IPC: H01L21/8234 ,  H01L27/088

Abstract: A method for fabricating a semiconductor device includes the steps of providing a substrate having a low-voltage (LV) region and a medium-voltage (MV) region, forming a first metal gate on the LV region and a second metal gate on the MV region, forming a first patterned mask on the second metal gate, removing part of the first metal gate, forming a second patterned mask on the first metal gate, removing part of the second metal gate, and then forming a first hard mask on the first metal gate and a second hard mask on the second metal gate.

公开(公告)号：US20240371855A1

公开(公告)日：2024-11-07

申请号：US18772301

申请日：2024-07-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Yu-Hsiang Lin ,  Chien-Ting Lin ,  Chia-Jung Hsu ,  Chun-Ya Chiu ,  Chin-Hung Chen

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region, a HV device on the HV region, and a LV device on the LV region. Preferably, the HV device includes a first base on the substrate, a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer. The LV device includes a fin-shaped structure on the substrate and a second gate electrode on the fin-shaped structure, in which a top surface of the first gate dielectric layer is lower than a top surface of the fin-shaped structure.

公开(公告)号：US20240315095A1

公开(公告)日：2024-09-19

申请号：US18135741

申请日：2023-04-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chuan-Lan Lin ,  Yu-Ping Wang ,  Chien-Ting Lin ,  Chu-Fu Lin ,  Chun-Ting Yeh ,  Chung-Hsing Kuo ,  Yi-Feng Hsu

IPC: H10K59/131

CPC classification number: H10K59/131

Abstract: A semiconductor device includes a substrate having a bonding area and a pad area, a first inter-metal dielectric (IMD) layer on the substrate, a metal interconnection in the first IMD layer, a first pad on the bonding area and connected to the metal interconnection, and a second pad on the pad area and connected to the metal interconnection. Preferably, the first pad includes a first portion connecting the metal interconnection and a second portion on the first portion, and the second pad includes a third portion connecting the metal interconnection and a fourth portion on the third portion, in which top surfaces of the second portion and the fourth portion are coplanar.

公开(公告)号：US20240162401A1

公开(公告)日：2024-05-16

申请号：US18078103

申请日：2022-12-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chuan-Lan Lin ,  Yu-Ping Wang ,  Chien-Ting Lin ,  Chun-Ting Yeh

IPC: H01L33/62 ,  H01L25/075

CPC classification number: H01L33/62 ,  H01L25/0753 ,  H01L2933/0066

Abstract: A method for fabricating a micro display device includes the steps of providing a wafer comprising a first area, a second area, and a third area, forming first bonding pads on the first area, forming second bonding pads on the second area, and forming third bonding pads on the third area. Preferably, the first bonding pads and the second bonding pads are made of different materials and the first bonding pads and the third bonding pads are made of different materials.

公开(公告)号：US11968910B2

公开(公告)日：2024-04-23

申请号：US17500971

申请日：2021-10-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Chan Lin ,  Yu-Ping Wang ,  Chien-Ting Lin

IPC: H10N52/01 ,  H10B61/00 ,  H10N52/00 ,  H10N52/80

CPC classification number: H10N52/01 ,  H10B61/00 ,  H10N52/00 ,  H10N52/80

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, forming an etch stop layer on the MTJ stack, forming a first spin orbit torque (SOT) layer on the etch stop layer, and then patterning the first SOT layer, the etch stop layer, and the MTJ stack to form a MTJ.

公开(公告)号：US20230268424A1

公开(公告)日：2023-08-24

申请号：US17706574

申请日：2022-03-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Jung Hsu ,  Ssu-I Fu ,  Chih-Kai Hsu ,  Chun-Ya Chiu ,  Chin-Hung Chen ,  Yu-Hsiang Lin ,  Chien-Ting Lin

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/762

CPC classification number: H01L29/66795 ,  H01L29/7851 ,  H01L29/0649 ,  H01L21/823431 ,  H01L21/762

Abstract: A method for fabricating a semiconductor device includes the steps of providing a substrate having a high-voltage (HV) region and a low-voltage (LV) region, forming first fin-shaped structures on the HV region, and then performing an oxidation process to form a gate oxide layer on and directly connecting the first fin-shaped structures. Preferably, a bottom surface of the gate oxide layer includes first bumps on the first fin-shaped structures while a top surface of the gate oxide layer includes second bumps.

公开(公告)号：US20220302374A1

公开(公告)日：2022-09-22

申请号：US17835986

申请日：2022-06-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-An Shih ,  Jing-Yin Jhang ,  I-Ming Tseng ,  Yu-Ping Wang ,  Chien-Ting Lin ,  Kun-Chen Ho ,  Yi-Syun Chou ,  Chang-Min Li ,  Yi-Wei Tseng ,  Yu-Tsung Lai ,  JUN XIE

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22

Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, a top electrode layer on the magnetic tunnel junction stack, and a hard mask layer on said top electrode layer, wherein the material of top electrode layer is titanium nitride, a material of said hard mask layer is tantalum or tantalum nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.

公开(公告)号：US20210111334A1

公开(公告)日：2021-04-15

申请号：US17131767

申请日：2020-12-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-An Shih ,  Jing-Yin Jhang ,  I-Ming Tseng ,  Yu-Ping Wang ,  Chien-Ting Lin ,  Kun-Chen Ho ,  Yi-Syun Chou ,  Chang-Min Li ,  Yi-Wei Tseng ,  Yu-Tsung Lai ,  JUN XIE

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22

Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, and a top electrode layer on the magnetic tunnel junction stack, wherein the material of top electrode layer is titanium nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.

公开(公告)号：US20210020828A1

公开(公告)日：2021-01-21

申请号：US16531129

申请日：2019-08-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-An Shih ,  Jing-Yin Jhang ,  I-Ming Tseng ,  Yu-Ping Wang ,  Chien-Ting Lin ,  Kun-Chen Ho ,  Yi-Syun Chou ,  Chang-Min Li ,  Yi-Wei Tseng ,  Yu-Tsung Lai ,  JUN XIE

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, and a top electrode layer on the magnetic tunnel junction stack, wherein the material of top electrode layer is titanium nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.

公开(公告)号：US10707135B2

公开(公告)日：2020-07-07

申请号：US15806277

申请日：2017-11-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Hao Tseng ,  Chien-Ting Lin ,  Shih-Hung Tsai ,  Po-Kuang Hsieh ,  Yu-Ting Tseng ,  Chueh-Fei Tai ,  Cheng-Ping Kuo

IPC: H01L21/00 ,  H01L21/8238 ,  H01L21/308 ,  H01L21/306 ,  H01L21/02 ,  H01L27/092 ,  H01L29/165 ,  H01L21/3065 ,  H01L29/66 ,  H01L29/167 ,  H01L21/762 ,  H01L21/266 ,  H01L21/265

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first well in the substrate on the first region and a second well in the substrate on the second region; removing part of the first well to form a first recess; and forming a first epitaxial layer in the first recess.