公开(公告)号：US20090166740A1

公开(公告)日：2009-07-02

申请号：US12006398

申请日：2007-12-31

申请人： Anup Bhalla ,  Xiaobin Wang ,  Wei Wang ,  Yi Su ,  Daniel Ng

发明人： Anup Bhalla ,  Xiaobin Wang ,  Wei Wang ,  Yi Su ,  Daniel Ng

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L29/06

CPC分类号： H01L29/7811 ,  H01L27/0255 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/66734 ,  H01L29/7808 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor power device supported on a semiconductor substrate includes an electrostatic discharge (ESD) protection circuit disposed on a first portion of patterned ESD polysilicon layer on top of the semiconductor substrate. The semiconductor power device further includes a second portion of the patterned ESD polysilicon layer constituting a body implant ion block layer for blocking implanting body ions to enter into the semiconductor substrate below the body implant ion block layer. In an exemplary embodiment, the electrostatic discharge (ESD) polysilicon layer on top of the semiconductor substrate further covering a scribe line on an edge of the semiconductor device whereby a passivation layer is no longer required manufacturing the semiconductor device for reducing a mask required for patterning the passivation layer.

摘要翻译： 支撑在半导体衬底上的半导体功率器件包括设置在半导体衬底顶部的图案化ESD多晶硅层的第一部分上的静电放电（ESD）保护电路。 该半导体功率器件还包括构图的ESD多晶硅层的第二部分，其构成体部注入离子阻挡层，用于阻止注入体离子进入体内注入离子阻挡层下方的半导体衬底。 在示例性实施例中，半导体衬底顶部上的静电放电（ESD）多晶硅层进一步覆盖半导体器件边缘上的划线，由此不再需要钝化层制造用于减少图案所需掩模的半导体器件 钝化层。

公开(公告)号：US09570404B2

公开(公告)日：2017-02-14

申请号：US14242851

申请日：2014-04-01

申请人： Ji Pang ,  Daniel Ng ,  Anup Bhalla ,  Xiaobin Wang

发明人： Ji Pang ,  Daniel Ng ,  Anup Bhalla ,  Xiaobin Wang

IPC分类号： H01L23/552 ,  H01L29/40 ,  H01L29/78 ,  H01L29/66 ,  H02M3/158 ,  H02M1/44

CPC分类号： H01L23/552 ,  H01L29/0638 ,  H01L29/401 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66704 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7823 ,  H01L29/7825 ,  H02M1/44 ,  H02M3/158

摘要： A semiconductor power device comprises a plurality of power transistor cells each having a trenched gate disposed in a gate trench wherein the trenched gate comprising a shielding bottom electrode disposed in a bottom portion of the gate trench electrically insulated from a top gate electrode disposed in a top portion of the gate trench by an inter-electrode insulation layer. At least one of the transistor cells includes the shielding bottom electrode functioning as a source-connecting shielding bottom electrode electrically connected to a source electrode of the semiconductor power device and at least one of the transistor cells having the shielding bottom electrode functioning as a gate-connecting shielding bottom electrode electrically connected to a gate metal of the semiconductor power device.

摘要翻译： 半导体功率器件包括多个功率晶体管单元，每个功率晶体管单元各自具有设置在栅极沟槽中的沟槽栅极，其中沟槽栅极包括设置在栅极沟槽的底部部分中的屏蔽底部电极，该顶部电极与设置在顶部的顶部栅极电绝缘 栅极沟槽的部分通过电极间绝缘层。 晶体管单元中的至少一个包括用作与半导体功率器件的源电极电连接的源极连接屏蔽底部电极的屏蔽底部电极，以及具有用作栅极连接的屏蔽底部电极的至少一个晶体管单元， 连接屏蔽底电极，电连接到半导体功率器件的栅极金属。

公开(公告)号：US08928079B2

公开(公告)日：2015-01-06

申请号：US13610758

申请日：2012-09-11

申请人： Anup Bhalla ,  Xiaobin Wang ,  Ji Pan ,  Sung-Po Wei

发明人： Anup Bhalla ,  Xiaobin Wang ,  Ji Pan ,  Sung-Po Wei

IPC分类号： H01L29/66 ,  H01L29/10 ,  H01L29/78 ,  H01L21/265 ,  H01L29/06 ,  H01L29/165 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/47

CPC分类号： H01L29/1095 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813

摘要： A semiconductor device is formed on a semiconductor substrate. The device includes: a drain; an epitaxial layer overlaying the drain, wherein a drain region extends into the epitaxial layer; and an active region. The active region includes: a body disposed in the epitaxial layer, having a body top surface; a source embedded in the body, extending from the body top surface into the body; a gate trench extending into the epitaxial layer; a gate disposed in the gate trench; an active region contact trench extending through the source and into the body; and an active region contact electrode disposed within the active region contact trench. A layer of body region separates the active region contact electrode from the epitaxial layer, and a low injection diode is formed below a body/drain junction.

摘要翻译： 半导体器件形成在半导体衬底上。 该装置包括：排水管; 覆盖所述漏极的外延层，其中漏区延伸到所述外延层中; 和活跃区域。 有源区包括：设置在外延层中的具有主体顶表面的主体; 嵌入在体内的源体，从身体顶面延伸到体内; 延伸到外延层中的栅极沟槽; 设置在栅极沟槽中的栅极; 有源区接触沟槽延伸穿过该源并进入体内; 以及设置在有源区接触沟槽内的有源区接触电极。 主体区域将有源区接触电极与外延层分开，并且在主体/漏极结下方形成低注入二极管。

公开(公告)号：US08642429B2

公开(公告)日：2014-02-04

申请号：US13537493

申请日：2012-06-29

申请人： Xiaobin Wang ,  Anup Bhalla ,  Yeeherg Lee

发明人： Xiaobin Wang ,  Anup Bhalla ,  Yeeherg Lee

IPC分类号： H01L21/336 ,  H01L27/088

CPC分类号： H01L29/0657 ,  H01L21/76202 ,  H01L21/76224 ,  H01L21/76227 ,  H01L29/407 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device structure with an oxide-filled large deep trench (OFLDT) portion having trench size TCS and trench depth TCD is disclosed. A bulk semiconductor layer (BSL) is provided with a thickness BSLT>TCD. A large trench top area (LTTA) is mapped out atop BSL with its geometry equal to OFLDT. The LTTA is partitioned into interspersed, complementary interim areas ITA-A and ITA-B. Numerous interim vertical trenches of depth TCD are created into the top BSL surface by removing bulk semiconductor materials corresponding to ITA-B. The remaining bulk semiconductor materials corresponding to ITA-A are converted into oxide. If any residual space is still left between the so-converted ITA-A, the residual space is filled up with oxide deposition. Importantly, the geometry of all ITA-A and ITA-B should be configured simple and small enough to facilitate fast and efficient processes of oxide conversion and oxide filling.

摘要翻译： 公开了具有沟槽尺寸TCS和沟槽深度TCD的具有氧化物填充的大深沟槽（OFLDT）部分的半导体器件结构。 体积半导体层（BSL）设置有厚度BSLT> TCD。 一个大的沟槽顶部区域（LTTA）映射到BSL顶部，其几何形状等于OFLDT。 LTTA被划分为散置的，互补的临时区域ITA-A和ITA-B。 通过去除对应于ITA-B的散装半导体材料，在顶部BSL表面上形成了许多深度TCD的临时垂直沟槽。 对应于ITA-A的剩余体积半导体材料被转化为氧化物。 如果在经过转换的ITA-A之间仍然留有剩余空间，则剩余空间被氧化物沉积填满。 重要的是，所有ITA-A和ITA-B的几何形状都应该被简单而小型化，以便于快速有效地进行氧化物转换和氧化物填充。

公开(公告)号：US20130328121A1

公开(公告)日：2013-12-12

申请号：US13490138

申请日：2012-06-06

申请人： Xiaobin Wang ,  Anup Bhalla ,  Daniel Ng

发明人： Xiaobin Wang ,  Anup Bhalla ,  Daniel Ng

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/42 ,  H01L29/408 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66734

摘要： A semiconductor power device includes a thick bottom insulator formed in a lower portion of a trench in a semiconductor epitaxial region. An electrically conductive gate electrode is formed in the trench above the bottom insulator. The gate electrode is electrically insulated from the epitaxial region by the bottom insulator and a gate insulator. Charge is deliberately induced in the thick bottom insulator proximate an interface between the bottom insulator and the epitaxial semiconductor region. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

摘要翻译： 半导体功率器件包括形成在半导体外延区域中的沟槽的下部的厚的底部绝缘体。 在底部绝缘体上方的沟槽中形成导电栅电极。 栅极电极通过底部绝缘体和栅极绝缘体与外延区域电绝缘。 在底部绝缘体和外延半导体区域之间的界面附近的厚底层绝缘体中有意地引起电荷。 要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

公开(公告)号：US08399925B2

公开(公告)日：2013-03-19

申请号：US12704528

申请日：2010-02-12

申请人： Xiaobin Wang ,  Anup Bhalla ,  Hamza Yilmaz ,  Daniel Ng

发明人： Xiaobin Wang ,  Anup Bhalla ,  Hamza Yilmaz ,  Daniel Ng

IPC分类号： H01L29/66

CPC分类号： H01L29/407 ,  H01L21/76205 ,  H01L29/04 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

摘要： A termination structure with multiple embedded potential spreading capacitive structures (TSMEC) and method are disclosed for terminating an adjacent trench MOSFET atop a bulk semiconductor layer (BSL) with bottom drain electrode. The BSL has a proximal bulk semiconductor wall (PBSW) supporting drain-source voltage (DSV) and separating TSMEC from trench MOSFET. The TSMEC has oxide-filled large deep trench (OFLDT) bounded by PBSW and a distal bulk semiconductor wall (DBSW). The OFLDT includes a large deep oxide trench into the BSL and embedded capacitive structures (EBCS) located inside the large deep oxide trench and between PBSW and DBSW for spatially spreading the DSV across them. In one embodiment, the EBCS contains interleaved conductive embedded polycrystalline semiconductor regions (EPSR) and oxide columns (OXC) of the OFLDT, a proximal EPSR next to PBSW is connected to an active upper source region and a distal EPSR next to DBSW is connected to the DBSW.

摘要翻译： 公开了具有多个嵌入式电位扩展电容结构（TSMEC）和方法的端接结构，用于在具有底部漏电极的体半导体层（BSL）的顶部端接邻近的沟槽MOSFET。 BSL具有支持漏极 - 源极电压（DSV）的近端体半导体壁（PBSW），并将TSMEC与沟槽MOSFET分离。 TSMEC具有由PBSW和远端体半导体壁（DBSW）界定的氧化物填充的大深沟槽（OFLDT）。 OFLDT包括位于大深度氧化物沟槽内部以及PBSW和DBSW之间的BSL中的大型深层氧化物沟槽和嵌入式电容结构（EBCS），用于在其间空间扩展DSV。 在一个实施例中，EBCS包含OFLDT的交错导电嵌入式多晶半导体区域（EPSR）和氧化物柱（OXC），与PBSW相邻的近端EPSR连接到活动上部源区域，并且与DBSW相邻的远端EPSR被连接到 星展集团

公开(公告)号：US20130009238A1

公开(公告)日：2013-01-10

申请号：US13349288

申请日：2012-01-12

申请人： Anup Bhalla ,  Xiaobin Wang ,  Moses Ho

发明人： Anup Bhalla ,  Xiaobin Wang ,  Moses Ho

IPC分类号： H01L27/06 ,  H01L21/329

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/872

摘要： This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region.

摘要翻译： 本发明公开了一种包括具有多个功率晶体管单元的有源单元区域的半导体功率器件。 每个所述功率晶体管单元具有平面肖特基二极管，其包括覆盖两个相邻功率晶体管单元之间的分离体区域之间的间隙上方的区域的肖特基结阻挡金属。 分离体区域还提供调节每个所述功率晶体管单元中的所述肖特基二极管的漏电流的功能。 每个平面肖特基二极管还包括设置在两个相邻功率晶体管单元的分离的体区之间的间隙中的香农注入区，用于进一步调整所述肖特基二极管的漏电流。 每个功率晶体管单元进一步包括分离体区域中的重体掺杂区域，其邻近形成结屏障肖特基（JBS）口袋区域的围绕所述肖特基二极管的源极区域。

公开(公告)号：US08283723B2

公开(公告)日：2012-10-09

申请号：US12005130

申请日：2007-12-21

申请人： Anup Bhalla ,  Xiaobin Wang ,  Ji Pan ,  Sung-Po Wei

发明人： Anup Bhalla ,  Xiaobin Wang ,  Ji Pan ,  Sung-Po Wei

IPC分类号： H01L29/66

CPC分类号： H01L29/1095 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813

摘要： A semiconductor device is formed on a semiconductor substrate. The device includes a drain, an epitaxial layer overlaying the drain, and an active region. The active region includes a body disposed in the epitaxial layer, having a body top surface, a source embedded in the body, extending from the body top surface into the body, a gate trench extending into the epitaxial layer, a gate disposed in the gate trench, an active region contact trench extending through the source and into the body, an active region contact electrode disposed within the active region contact trench, wherein a thin layer of body region separating the active region contact electrode from the drain.

摘要翻译： 半导体器件形成在半导体衬底上。 该器件包括漏极，覆盖漏极的外延层和有源区。 所述有源区包括设置在所述外延层中的主体，具有主体顶表面，嵌入在所述主体中的源，从所述主体顶表面延伸到所述主体中，延伸到所述外延层中的栅沟槽，设置在所述栅极中的栅极 沟槽，延伸穿过源极并进入主体的有源区接触沟槽，设置在有源区接触沟槽内的有源区接触电极，其中将有源区接触电极与漏极分离的体区的薄层。

公开(公告)号：US20120080751A1

公开(公告)日：2012-04-05

申请号：US13316365

申请日：2011-12-09

申请人： Anup Bhalla ,  Xiaobin Wang ,  Ji Pan ,  Sung-Po Wei

发明人： Anup Bhalla ,  Xiaobin Wang ,  Ji Pan ,  Sung-Po Wei

IPC分类号： H01L27/092

CPC分类号： H01L29/66484 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813

摘要： A semiconductor device is formed on a semiconductor substrate. The device comprises a drain; an epitaxial layer overlaying the drain; a body disposed in the epitaxial layer, having a body top surface and a body bottom surface; a source embedded in the body, extending from the body top surface into the body; a first gate trench extending into the epitaxial layer; a first gate disposed in the first gate trench; an active region contact trench extending through the source and at least part of the body into the drain; an active region contact electrode disposed within the active region contact trench; a second gate trench extending into the epitaxial layer; a second gate disposed in the gate trench; a gate contact trench formed within the second gate; and a gate contact electrode disposed within the gate contact trench.

摘要翻译： 半导体器件形成在半导体衬底上。 该装置包括排水管; 覆盖漏极的外延层; 设置在外延层中的主体，具有主体顶表面和主体底表面; 嵌入在体内的源体，从身体顶面延伸到体内; 延伸到所述外延层中的第一栅极沟槽; 设置在所述第一栅极沟槽中的第一栅极; 有源区域接触沟槽，其延伸穿过源极和至少部分本体进入漏极; 有源区接触电极，设置在有源区接触沟槽内; 延伸到所述外延层中的第二栅极沟槽; 设置在所述栅极沟槽中的第二栅极; 形成在第二栅极内的栅极接触沟槽; 以及设置在所述栅极接触沟槽内的栅极接触电极。

公开(公告)号：US20110210390A1

公开(公告)日：2011-09-01

申请号：US13088275

申请日：2011-04-15

申请人： Anup Bhalla ,  Xiaobin Wang

发明人： Anup Bhalla ,  Xiaobin Wang

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811

摘要： A semiconductor device includes a drain region comprising an epitaxial layer, a body disposed in the epitaxial layer, a source embedded in the body, a gate trench extending into the epitaxial layer, a gate disposed in the gate trench, an active region contact trench extending through the source, and an active region contact electrode disposed within the active region contact trench. The active region contact trench has a first width associated with a first region that is in proximity to a bottom portion of the body and a second width associated with a second region that is in proximity to a bottom portion of the source. The first width is substantially different from the second width.

摘要翻译： 半导体器件包括：漏区，包括外延层，设置在外延层中的主体，嵌入在主体中的源极，延伸到外延层中的栅极沟槽，设置在栅极沟槽中的栅极，有源区域接触沟槽延伸 通过源极，以及设置在有源区接触沟槽内的有源区接触电极。 有源区接触沟槽具有与位于本体底部附近的第一区域相关联的第一宽度和与源极底部附近的第二区域相关联的第二宽度。 第一宽度与第二宽度大致不同。