公开(公告)号：US20140167212A1

公开(公告)日：2014-06-19

申请号：US13712980

申请日：2012-12-13

申请人： Xiaobin Wang ,  Anup Bhalla ,  Hamza Yilmaz ,  Daniel Ng

发明人： Xiaobin Wang ,  Anup Bhalla ,  Hamza Yilmaz ,  Daniel Ng

IPC分类号： H01L21/762 ,  H01L29/06

CPC分类号： H01L29/407 ,  H01L21/76205 ,  H01L29/04 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

摘要： A termination structure with multiple embedded potential spreading capacitive structures (TSMEC) and method are disclosed for terminating an adjacent trench MOSFET atop a bulk semiconductor layer (BSL) with bottom drain electrode. The BSL has a proximal bulk semiconductor wall (PBSW) supporting drain-source voltage (DSV) and separating TSMEC from trench MOSFET. The TSMEC has oxide-filled large deep trench (OFLDT) bounded by PBSW and a distal bulk semiconductor wall (DBSW). The OFLDT includes a large deep oxide trench into the BSL and embedded capacitive structures (EBCS) located inside the large deep oxide trench and between PBSW and DBSW for spatially spreading the DSV across them. In one embodiment, the EBCS contains interleaved conductive embedded polycrystalline semiconductor regions (EPSR) and oxide columns (OXC) of the OFLDT, a proximal EPSR next to PBSW is connected to an active upper source region and a distal EPSR next to DBSW is connected to the DBSW.

摘要翻译： 公开了具有多个嵌入式电位扩展电容结构（TSMEC）和方法的端接结构，用于在具有底部漏电极的体半导体层（BSL）的顶部端接邻近的沟槽MOSFET。 BSL具有支持漏极 - 源极电压（DSV）的近端体半导体壁（PBSW），并将TSMEC与沟槽MOSFET分离。 TSMEC具有由PBSW和远端体半导体壁（DBSW）界定的氧化物填充的大深沟槽（OFLDT）。 OFLDT包括位于大深度氧化物沟槽内部以及PBSW和DBSW之间的BSL中的大型深层氧化物沟槽和嵌入式电容结构（EBCS），用于在其间空间扩展DSV。 在一个实施例中，EBCS包含OFLDT的交错导电嵌入式多晶半导体区域（EPSR）和氧化物柱（OXC），与PBSW相邻的近端EPSR连接到活动上部源区域，并且与DBSW相邻的远端EPSR被连接到 星展集团

公开(公告)号：US20110198605A1

公开(公告)日：2011-08-18

申请号：US12704528

申请日：2010-02-12

申请人： Xiaobin Wang ,  Anup Bhalla ,  Hamza Yilmaz ,  Daniel Ng

发明人： Xiaobin Wang ,  Anup Bhalla ,  Hamza Yilmaz ,  Daniel Ng

IPC分类号： H01L29/94 ,  H01L21/02

CPC分类号： H01L29/407 ,  H01L21/76205 ,  H01L29/04 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

摘要： A termination structure with multiple embedded potential spreading capacitive structures (TSMEC) and method are disclosed for terminating an adjacent trench MOSFET atop a bulk semiconductor layer (BSL) with bottom drain electrode. The BSL has a proximal bulk semiconductor wall (PBSW) supporting drain-source voltage (DSV) and separating TSMEC from trench MOSFET. The TSMEC has oxide-filled large deep trench (OFLDT) bounded by PBSW and a distal bulk semiconductor wall (DBSW). The OFLDT includes a large deep oxide trench into the BSL and embedded capacitive structures (EBCS) located inside the large deep oxide trench and between PBSW and DBSW for spatially spreading the DSV across them. In one embodiment, the EBCS contains interleaved conductive embedded polycrystalline semiconductor regions (EPSR) and oxide columns (OXC) of the OFLDT, a proximal EPSR next to PBSW is connected to an active upper source region and a distal EPSR next to DBSW is connected to the DBSW.

摘要翻译： 公开了具有多个嵌入式电位扩展电容结构（TSMEC）和方法的端接结构，用于在具有底部漏电极的体半导体层（BSL）的顶部端接邻近的沟槽MOSFET。 BSL具有支持漏极 - 源极电压（DSV）的近端体半导体壁（PBSW），并将TSMEC与沟槽MOSFET分离。 TSMEC具有由PBSW和远端体半导体壁（DBSW）界定的氧化物填充的大深沟槽（OFLDT）。 OFLDT包括位于大深度氧化物沟槽内部以及PBSW和DBSW之间的BSL中的大型深层氧化物沟槽和嵌入式电容结构（EBCS），用于在其间空间扩展DSV。 在一个实施例中，EBCS包含OFLDT的交错导电嵌入式多晶半导体区域（EPSR）和氧化物柱（OXC），与PBSW相邻的近端EPSR连接到活动上部源区域，并且与DBSW相邻的远端EPSR被连接到 星展集团

公开(公告)号：US08399925B2

公开(公告)日：2013-03-19

申请号：US12704528

申请日：2010-02-12

申请人： Xiaobin Wang ,  Anup Bhalla ,  Hamza Yilmaz ,  Daniel Ng

发明人： Xiaobin Wang ,  Anup Bhalla ,  Hamza Yilmaz ,  Daniel Ng

IPC分类号： H01L29/66

CPC分类号： H01L29/407 ,  H01L21/76205 ,  H01L29/04 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

摘要： A termination structure with multiple embedded potential spreading capacitive structures (TSMEC) and method are disclosed for terminating an adjacent trench MOSFET atop a bulk semiconductor layer (BSL) with bottom drain electrode. The BSL has a proximal bulk semiconductor wall (PBSW) supporting drain-source voltage (DSV) and separating TSMEC from trench MOSFET. The TSMEC has oxide-filled large deep trench (OFLDT) bounded by PBSW and a distal bulk semiconductor wall (DBSW). The OFLDT includes a large deep oxide trench into the BSL and embedded capacitive structures (EBCS) located inside the large deep oxide trench and between PBSW and DBSW for spatially spreading the DSV across them. In one embodiment, the EBCS contains interleaved conductive embedded polycrystalline semiconductor regions (EPSR) and oxide columns (OXC) of the OFLDT, a proximal EPSR next to PBSW is connected to an active upper source region and a distal EPSR next to DBSW is connected to the DBSW.

摘要翻译： 公开了具有多个嵌入式电位扩展电容结构（TSMEC）和方法的端接结构，用于在具有底部漏电极的体半导体层（BSL）的顶部端接邻近的沟槽MOSFET。 BSL具有支持漏极 - 源极电压（DSV）的近端体半导体壁（PBSW），并将TSMEC与沟槽MOSFET分离。 TSMEC具有由PBSW和远端体半导体壁（DBSW）界定的氧化物填充的大深沟槽（OFLDT）。 OFLDT包括位于大深度氧化物沟槽内部以及PBSW和DBSW之间的BSL中的大型深层氧化物沟槽和嵌入式电容结构（EBCS），用于在其间空间扩展DSV。 在一个实施例中，EBCS包含OFLDT的交错导电嵌入式多晶半导体区域（EPSR）和氧化物柱（OXC），与PBSW相邻的近端EPSR连接到活动上部源区域，并且与DBSW相邻的远端EPSR被连接到 星展集团

公开(公告)号：US08247329B2

公开(公告)日：2012-08-21

申请号：US13024256

申请日：2011-02-09

申请人： Hamza Yilmaz ,  Xiaobin Wang ,  Anup Bhalla ,  John Chen ,  Hong Chang

发明人： Hamza Yilmaz ,  Xiaobin Wang ,  Anup Bhalla ,  John Chen ,  Hong Chang

IPC分类号： H01L21/311

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0692 ,  H01L29/1095 ,  H01L29/6609 ,  H01L29/66143 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/7397 ,  H01L29/861 ,  H01L29/872

摘要： A method for forming a semiconductor device includes forming a nanotube region using a thin epitaxial layer formed on the sidewall of a trench in the semiconductor body. The thin epitaxial layer has uniform doping concentration. In another embodiment, a first thin epitaxial layer of the same conductivity type as the semiconductor body is formed on the sidewall of a trench in the semiconductor body and a second thin epitaxial layer of the opposite conductivity type is formed on the first epitaxial layer. The first and second epitaxial layers have uniform doping concentration. The thickness and doping concentrations of the first and second epitaxial layers and the semiconductor body are selected to achieve charge balance. In one embodiment, the semiconductor body is a lightly doped P-type substrate. A vertical trench MOSFET, an IGBT, a Schottky diode and a P-N junction diode can be formed using the same N-Epi/P-Epi nanotube structure.

摘要翻译： 形成半导体器件的方法包括：使用形成在半导体本体中的沟槽的侧壁上的薄外延层来形成纳米管区域。 薄的外延层具有均匀的掺杂浓度。 在另一个实施例中，在半导体主体中的沟槽的侧壁上形成与半导体本体相同的导电类型的第一薄外延层，并且在第一外延层上形成相反导电类型的第二薄外延层。 第一和第二外延层具有均匀的掺杂浓度。 选择第一和第二外延层和半导体本体的厚度和掺杂浓度以实现电荷平衡。 在一个实施例中，半导体本体是轻掺杂的P型衬底。 可以使用相同的N-Epi / P-Epi纳米管结构来形成垂直沟槽MOSFET，IGBT，肖特基二极管和P-N结二极管。

公开(公告)号：US07910486B2

公开(公告)日：2011-03-22

申请号：US12484166

申请日：2009-06-12

申请人： Hamza Yilmaz ,  Xiaobin Wang ,  Anup Bhalla ,  John Chen ,  Hong Chang

发明人： Hamza Yilmaz ,  Xiaobin Wang ,  Anup Bhalla ,  John Chen ,  Hong Chang

IPC分类号： H01L21/311

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0692 ,  H01L29/1095 ,  H01L29/6609 ,  H01L29/66143 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/7397 ,  H01L29/861 ,  H01L29/872

摘要： A method for forming a semiconductor device includes forming a nanotube region using a thin epitaxial layer formed on the sidewall of a trench in the semiconductor body. The thin epitaxial layer has uniform doping concentration. In another embodiment, a first thin epitaxial layer of the same conductivity type as the semiconductor body is formed on the sidewall of a trench in the semiconductor body and a second thin epitaxial layer of the opposite conductivity type is formed on the first epitaxial layer. The first and second epitaxial layers have uniform doping concentration. The thickness and doping concentrations of the first and second epitaxial layers and the semiconductor body are selected to achieve charge balance. In one embodiment, the semiconductor body is a lightly doped P-type substrate. A vertical trench MOSFET, an IGBT, a Schottky diode and a P-N junction diode can be formed using the same N-Epi/P-Epi nanotube structure.

摘要翻译： 形成半导体器件的方法包括：使用形成在半导体本体中的沟槽的侧壁上的薄外延层来形成纳米管区域。 薄的外延层具有均匀的掺杂浓度。 在另一个实施例中，在半导体主体中的沟槽的侧壁上形成与半导体本体相同的导电类型的第一薄外延层，并且在第一外延层上形成相反导电类型的第二薄外延层。 第一和第二外延层具有均匀的掺杂浓度。 选择第一和第二外延层和半导体本体的厚度和掺杂浓度以实现电荷平衡。 在一个实施例中，半导体本体是轻掺杂的P型衬底。 可以使用相同的N-Epi / P-Epi纳米管结构形成垂直沟槽MOSFET，IGBT，肖特基二极管和P-N结二极管。

公开(公告)号：US20100314682A1

公开(公告)日：2010-12-16

申请号：US12661004

申请日：2010-03-05

申请人： Hamza Yilmaz ,  Madhur Bobde ,  Yeeheng Lee ,  Lingpeng Guan ,  Xiaobin Wang ,  John Chen ,  Anup Bhalla

发明人： Hamza Yilmaz ,  Madhur Bobde ,  Yeeheng Lee ,  Lingpeng Guan ,  Xiaobin Wang ,  John Chen ,  Anup Bhalla

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/762

CPC分类号： H01L29/7397 ,  H01L29/0661 ,  H01L29/66348

摘要： This invention discloses semiconductor power device disposed on a semiconductor substrate of a first conductivity type. The semiconductor substrate supports an epitaxial layer of a second conductivity type thereon wherein the semiconductor power device is supported on a super-junction structure. The super-junction structure comprises a plurality of trenches opened from a top surface in the epitaxial layer; wherein each of the trenches having trench sidewalls covered with a first epitaxial layer of the first conductivity type to counter charge the epitaxial layer of the second conductivity type. A second epitaxial layer may be grown over the first epitaxial layer. Each of the trenches is filled with a non-doped dielectric material in a remaining trench gap space. Each of the trench sidewalls is opened with a tilted angle to form converging U-shaped trenches.

摘要翻译： 本发明公开了一种设置在第一导电类型的半导体衬底上的半导体功率器件。 半导体衬底在其上支撑第二导电类型的外延层，其中半导体功率器件被支撑在超结结构上。 超结结构包括从外延层中的顶表面开放的多个沟槽; 其中每个沟槽具有覆盖有第一导电类型的第一外延层的沟槽侧壁，以对第二导电类型的外延层进行反电荷充电。 可以在第一外延层上生长第二外延层。 每个沟槽在剩余沟槽间隙空间中填充有非掺杂电介质材料。 每个沟槽侧壁以倾斜角打开以形成会聚的U形沟槽。

公开(公告)号：US08299494B2

公开(公告)日：2012-10-30

申请号：US12484170

申请日：2009-06-12

申请人： Hamza Yilmaz ,  Xiaobin Wang ,  Anup Bhalla ,  John Chen ,  Hong Chang

发明人： Hamza Yilmaz ,  Xiaobin Wang ,  Anup Bhalla ,  John Chen ,  Hong Chang

IPC分类号： H01L29/74 ,  H01L31/111 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/0886 ,  H01L21/26586 ,  H01L27/0623 ,  H01L27/0629 ,  H01L27/0664 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0676 ,  H01L29/0688 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/365 ,  H01L29/402 ,  H01L29/404 ,  H01L29/41741 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7803 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/861 ,  H01L29/8613 ,  H01L29/872 ,  H01L29/8725

摘要： A semiconductor device includes a first semiconductor layer and a second semiconductor layer of opposite conductivity type, a first epitaxial layer of the first conductivity type formed on sidewalls of the trenches, and a second epitaxial layer of the second conductivity type formed on the first epitaxial layer where the second epitaxial layer is electrically connected to the second semiconductor layer. The first epitaxial layer and the second epitaxial layer form parallel doped regions along the sidewalls of the trenches, each having uniform doping concentration. The second epitaxial layer has a first thickness and a first doping concentration and the first epitaxial layer and a mesa of the first semiconductor layer together having a second thickness and a second average doping concentration where the first and second thicknesses and the first doping concentration and second average doping concentrations are selected to achieve charge balance in operation.

摘要翻译： 半导体器件包括第一半导体层和相反导电类型的第二半导体层，形成在沟槽的侧壁上的第一导电类型的第一外延层和形成在第一外延层上的第二导电类型的第二外延层 其中第二外延层电连接到第二半导体层。 第一外延层和第二外延层沿着沟槽的侧壁形成平行的掺杂区域，每个具有均匀的掺杂浓度。 第二外延层具有第一厚度和第一掺杂浓度，第一外延层和第一半导体层的台面一起具有第二厚度和第二平均掺杂浓度，其中第一和第二厚度和第一掺杂浓度和第二掺杂浓度 选择平均掺杂浓度以在操作中实现电荷平衡。

公开(公告)号：US20100317158A1

公开(公告)日：2010-12-16

申请号：US12484166

申请日：2009-06-12

申请人： Hamza Yilmaz ,  Xiaobin Wang ,  Anup Bhalla ,  John Chen ,  Hong Chang

发明人： Hamza Yilmaz ,  Xiaobin Wang ,  Anup Bhalla ,  John Chen ,  Hong Chang

IPC分类号： H01L21/336 ,  H01L21/331 ,  H01L21/329

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0692 ,  H01L29/1095 ,  H01L29/6609 ,  H01L29/66143 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/7397 ,  H01L29/861 ,  H01L29/872

摘要： A method for forming a semiconductor device includes forming a nanotube region using a thin epitaxial layer formed on the sidewall of a trench in the semiconductor body. The thin epitaxial layer has uniform doping concentration. In another embodiment, a first thin epitaxial layer of the same conductivity type as the semiconductor body is formed on the sidewall of a trench in the semiconductor body and a second thin epitaxial layer of the opposite conductivity type is formed on the first epitaxial layer. The first and second epitaxial layers have uniform doping concentration. The thickness and doping concentrations of the first and second epitaxial layers and the semiconductor body are selected to achieve charge balance. In one embodiment, the semiconductor body is a lightly doped P-type substrate. A vertical trench MOSFET, an IGBT, a Schottky diode and a P-N junction diode can be formed using the same N-Epi/P-Epi nanotube structure.

摘要翻译： 形成半导体器件的方法包括：使用形成在半导体本体中的沟槽的侧壁上的薄外延层来形成纳米管区域。 薄的外延层具有均匀的掺杂浓度。 在另一个实施例中，在半导体主体中的沟槽的侧壁上形成与半导体本体相同的导电类型的第一薄外延层，并且在第一外延层上形成相反导电类型的第二薄外延层。 第一和第二外延层具有均匀的掺杂浓度。 选择第一和第二外延层和半导体本体的厚度和掺杂浓度以实现电荷平衡。 在一个实施例中，半导体本体是轻掺杂的P型衬底。 可以使用相同的N-Epi / P-Epi纳米管结构形成垂直沟槽MOSFET，IGBT，肖特基二极管和P-N结二极管。

公开(公告)号：US20100314659A1

公开(公告)日：2010-12-16

申请号：US12484170

申请日：2009-06-12

申请人： Hamza Yilmaz ,  Xiaobin Wang ,  Anup Bhalla ,  John Chen ,  Hong Chang

发明人： Hamza Yilmaz ,  Xiaobin Wang ,  Anup Bhalla ,  John Chen ,  Hong Chang

IPC分类号： H01L29/739 ,  H01L29/78

CPC分类号： H01L29/0886 ,  H01L21/26586 ,  H01L27/0623 ,  H01L27/0629 ,  H01L27/0664 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0676 ,  H01L29/0688 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/365 ,  H01L29/402 ,  H01L29/404 ,  H01L29/41741 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7803 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/861 ,  H01L29/8613 ,  H01L29/872 ,  H01L29/8725

摘要： A semiconductor device includes a first semiconductor layer and a second semiconductor layer of opposite conductivity type, a first epitaxial layer of the first conductivity type formed on sidewalls of the trenches, and a second epitaxial layer of the second conductivity type formed on the first epitaxial layer where the second epitaxial layer is electrically connected to the second semiconductor layer. The first epitaxial layer and the second epitaxial layer form parallel doped regions along the sidewalls of the trenches, each having uniform doping concentration. The second epitaxial layer has a first thickness and a first doping concentration and the first epitaxial layer and a mesa of the first semiconductor layer together having a second thickness and a second average doping concentration where the first and second thicknesses and the first doping concentration and second average doping concentrations are selected to achieve charge balance in operation.

摘要翻译： 半导体器件包括第一半导体层和相反导电类型的第二半导体层，形成在沟槽的侧壁上的第一导电类型的第一外延层和形成在第一外延层上的第二导电类型的第二外延层 其中第二外延层电连接到第二半导体层。 第一外延层和第二外延层沿着沟槽的侧壁形成平行的掺杂区域，每个具有均匀的掺杂浓度。 第二外延层具有第一厚度和第一掺杂浓度，第一外延层和第一半导体层的台面一起具有第二厚度和第二平均掺杂浓度，其中第一和第二厚度和第一掺杂浓度和第二掺杂浓度 选择平均掺杂浓度以在操作中实现电荷平衡。

公开(公告)号：US08390058B2

公开(公告)日：2013-03-05

申请号：US12661004

申请日：2010-03-05

申请人： Hamza Yilmaz ,  Madhur Bobde ,  Yeeheng Lee ,  Lingpeng Guan ,  Xiaobin Wang ,  John Chen ,  Anup Bhalla

发明人： Hamza Yilmaz ,  Madhur Bobde ,  Yeeheng Lee ,  Lingpeng Guan ,  Xiaobin Wang ,  John Chen ,  Anup Bhalla

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7397 ,  H01L29/0661 ,  H01L29/66348

摘要： This invention discloses semiconductor power device disposed on a semiconductor substrate of a first conductivity type. The semiconductor substrate supports an epitaxial layer of a second conductivity type thereon wherein the semiconductor power device is supported on a super-junction structure. The super-junction structure comprises a plurality of trenches opened from a top surface in the epitaxial layer; wherein each of the trenches having trench sidewalls covered with a first epitaxial layer of the first conductivity type to counter charge the epitaxial layer of the second conductivity type. A second epitaxial layer may be grown over the first epitaxial layer. Each of the trenches is filled with a non-doped dielectric material in a remaining trench gap space. Each of the trench sidewalls is opened with a tilted angle to form converging U-shaped trenches.

摘要翻译： 本发明公开了一种设置在第一导电类型的半导体衬底上的半导体功率器件。 半导体衬底在其上支撑第二导电类型的外延层，其中半导体功率器件被支撑在超结结构上。 超结结构包括从外延层中的顶表面开放的多个沟槽; 其中每个沟槽具有覆盖有第一导电类型的第一外延层的沟槽侧壁，以对第二导电类型的外延层进行反电荷充电。 可以在第一外延层上生长第二外延层。 每个沟槽在剩余沟槽间隙空间中填充有非掺杂电介质材料。 每个沟槽侧壁以倾斜角打开以形成会聚的U形沟槽。