公开(公告)号：US20050014326A1

公开(公告)日：2005-01-20

申请号：US10899119

申请日：2004-07-27

申请人： Takashi Kobayashi ,  Yasushi Goto ,  Tokuo Kure ,  Hideaki Kurata ,  Hitoshi Kume ,  Katsutaka Kimura ,  Syunichi Saeki

发明人： Takashi Kobayashi ,  Yasushi Goto ,  Tokuo Kure ,  Hideaki Kurata ,  Hitoshi Kume ,  Katsutaka Kimura ,  Syunichi Saeki

IPC分类号： H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42328 ,  H01L29/7881

摘要： A semiconductor integrated circuit device with third gates comprising second conduction type source/drain diffusion layer regions 205 formed first conduction type well 201, floating gates 203b formed on semiconductor substrate 200 through an insulator film 202, control gates 211a formed on floating gates 203b through nitrogen-introduced silicon oxide film 210a and third gates 207a different from the floating gates and the control gates, formed through the semiconductor substrates, the floating gates, the control gates and the insulator film, where the third gates are formed as filled in gaps between the floating gates existing in a vertical direction to word lines and channels and the height of third gates 207a thus formed is made lower than that of floating gates 203b, has improved reduction of memory cell size and operating speed and improved reliability after programming/erasing cycles.

摘要翻译： 具有第三栅极的半导体集成电路器件包括形成在第一导电型阱201的第二导电型源极/漏极扩散层区域205，通过绝缘膜202形成在半导体衬底200上的浮动栅极203b，通过氮气形成在浮动栅极203b上的控制栅极211a 引入与通过半导体衬底，浮动栅极，控制栅极和绝缘膜形成的浮动栅极和控制栅极不同的氧化硅膜210a和第三栅极207a，其中第三栅极形成为填充在第 存在于字线和沟道的垂直方向的浮动栅极和由此形成的第三栅极207a的高度低于浮置栅极203b的高度，改善了编程/擦除周期后存储单元尺寸和操作速度的降低以及改进的可靠性。

公开(公告)号：US06798696B2

公开(公告)日：2004-09-28

申请号：US10364417

申请日：2003-02-12

申请人： Toru Matsushita ,  Hideaki Kurata ,  Naoki Kobayashi

发明人： Toru Matsushita ,  Hideaki Kurata ,  Naoki Kobayashi

IPC分类号： G11C1134

CPC分类号： G11C8/12 ,  G06F12/0246 ,  G06F2212/1016 ,  G06F2212/7202 ,  G06F2212/7208 ,  G11C16/06

摘要： Disclosed herewith is a method for controlling the operation of non-volatile semiconductor chips with high sequential access performance realized by smoothing out the variation of the times for writing, erasing, and reading data in/from memory cells among sectors in each of the chips.

摘要翻译： 这里公开了一种用于通过平滑每个芯片中的扇区中的/从存储器单元中写入，擦除和读取数据的时间的变化而实现的具有高顺序访问性能的非易失性半导体芯片的操作的方法。

公开(公告)号：US06552765B2

公开(公告)日：2003-04-22

申请号：US09423644

申请日：1999-11-18

申请人： Hideaki Kurata

发明人： Hideaki Kurata

IPC分类号： G02F11335

CPC分类号： G02F1/133516 ,  G02B5/201 ,  G02F1/133514 ,  G02F2203/02

摘要： Provided is a color filter 29 for reflection-type liquid crystal display devices, which comprises a light-reflecting layer 22, a transparent electrode 23, and a colorant layer 24 with electroconductive grains therein, as laminated in that order on a transparent or opaque substrate 21. Also provided is a reflection-type liquid crystal display device comprising the color filter, in which a substrate 27 having a transparent electrode 26 formed thereon is so combined with the color filter that the transparent electrode 26 faces the light input side of the color filter via a liquid crystal layer 25 existing therebetween. With that constitution, the device enjoys a broad angle of visibility and is not troubled by color drift (color mixing) The device can produce light images in light conditions.

摘要翻译： 提供了一种用于反射型液晶显示装置的滤色器29，其包括光反射层22，透明电极23和其中具有导电颗粒的着色层24，按顺序层叠在透明或不透明基板上 21.还提供了一种反射型液晶显示装置，其包括滤色器，其中在其上形成有透明电极26的基板27与滤色器结合，使得透明电极26面向颜色的光输入侧 通过其间存在的液晶层25过滤。 利用这种结构，该装置具有广泛的可见度，并且不会因颜色漂移（混色）而困扰。该装置可以在光照条件下产生光图像。

公开(公告)号：US06445615B2

公开(公告)日：2002-09-03

申请号：US09758221

申请日：2001-01-12

申请人： Naoki Kobayashi ,  Shunichi Saeki ,  Hideaki Kurata

发明人： Naoki Kobayashi ,  Shunichi Saeki ,  Hideaki Kurata

IPC分类号： G11C1604

CPC分类号： G11C7/1078 ,  G11C7/1087 ,  G11C8/12 ,  G11C16/08 ,  G11C16/10 ,  G11C2216/14

摘要： A non-volatile semiconductor memory device is capable of having its individual banks controlled separately from the outside, and a semiconductor disk device is capable of proceeding immediately to the next writing to a bank of non-volatile semiconductor memory device which has become ready. Each bank has the independent write operation of data from its data register to memory cells, enabling the transfer of data from the outside to the data register of the bank even during the write operation of other bank from the data register to memory cells thereof.

公开(公告)号：US20120123764A1

公开(公告)日：2012-05-17

申请号：US13387243

申请日：2010-07-16

申请人： Yasuhiro Ito ,  Yasuo Sugure ,  Shigeru Oho ,  Hideaki Kurata

发明人： Yasuhiro Ito ,  Yasuo Sugure ,  Shigeru Oho ,  Hideaki Kurata

IPC分类号： G06F17/50

CPC分类号： G06F11/3664 ,  G06F9/5055

摘要： The cost necessary for introducing and maintaining a development environment that includes multiple simulators is suppressed, and a sharing of designing information is promoted, to make parameter adjustment of simulators easy. Provided is a service that unifies development environment on a computer provided with: a working computer system that can guarantee that there is no leaking of designing files; a user behavior monitoring system that collects utilization history of simulators or software, for each of the users, and selects development process of each of the users from the collected information; and a dynamic computational-resource distribution system that can conduct an automatic optimization of a complex simulation configuration, from information collected by the aforementioned user behavior monitoring system.

摘要翻译： 引入和维护包含多个模拟器的开发环境所需的成本被抑制，并且提高了设计信息的共享，从而使模拟器的参数调整变得容易。 提供了一种将计算机上的开发环境统一起来的服务，它具有：可以保证设计文件不泄漏的工作计算机系统; 用户行为监控系统，用于为每个用户收集模拟器或软件的利用历史，并从收集的信息中选择每个用户的开发过程; 以及动态计算资源分配系统，可以从上述用户行为监控系统收集的信息中进行复杂模拟配置的自动优化。

公开(公告)号：US20110235386A1

公开(公告)日：2011-09-29

申请号：US13154113

申请日：2011-06-06

申请人： Tomoyuki Ishii ,  Yoshitaka Sasago ,  Hideaki Kurata ,  Toshiyuki Mine

发明人： Tomoyuki Ishii ,  Yoshitaka Sasago ,  Hideaki Kurata ,  Toshiyuki Mine

IPC分类号： G11C5/02

CPC分类号： H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

摘要： The invention provides a voltage applying structure having a reduced area penalty with respect to a data line. A wiring forming a global data line and a local data line formed in a p-type well region are connected via a select transistor. Two select lines are formed on a gate electrode of the select transistor. One select line is electrically connected to the gate electrode of the select transistor, however, the other select line is not connected to the select transistor. That is, an insulator film is formed between the select line and the gate electrode. As mentioned above, two select lines shorter than a gate length are provided on one select transistor. The select line is structured such as to be connected to the other select transistor.

摘要翻译： 本发明提供一种相对于数据线具有减小的面积损失的电压施加结构。 形成在p型阱区中的全局数据线和局部数据线的布线经由选择晶体管连接。 在选择晶体管的栅电极上形成两条选择线。 一个选择线电连接到选择晶体管的栅电极，然而另一选择线不连接到选择晶体管。 也就是说，在选择线和栅电极之间形成绝缘膜。 如上所述，在一个选择晶体管上设置两条比栅极长度短的选择线。 选择线被构造成连接到另一个选择晶体管。

公开(公告)号：US07323741B2

公开(公告)日：2008-01-29

申请号：US10998630

申请日：2004-11-30

申请人： Kazuo Otsuga ,  Hideaki Kurata ,  Yoshitaka Sasago

发明人： Kazuo Otsuga ,  Hideaki Kurata ,  Yoshitaka Sasago

IPC分类号： H01L29/788 ,  H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC分类号： H01L29/7885 ,  G11C11/5621 ,  G11C16/0433 ,  G11C16/0491 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42328

摘要： A low cost semiconductor nonvolatile memory device capable of high speed programming, using an inversion layer as the wiring, and a manufacturing method for that device. The semiconductor memory device includes an auxiliary electrode at a position between and in parallel with the source and drain regions and with no position overlap versus the source region and the drain region formed mutually in parallel; wherein the auxiliary electrode for hot electron source injection is utilized as the auxiliary electrode for programming (writing); and an inversion layer formed below the auxiliary electrode is utilized as the source region or as the drain region during the read operation.

摘要翻译： 能够使用反转层作为布线的能够进行高速编程的低成本半导体非易失性存储器件以及该器件的制造方法。 半导体存储器件包括在源极和漏极区域之间并与之平行的位置处的辅助电极，并且与相互平行形成的源极区域和漏极区域没有位置重叠; 其中用于热电子源注入的辅助电极用作编程（写入）的辅助电极; 并且在读取操作期间，在辅助电极下形成的反型层用作源极区域或漏极区域。

公开(公告)号：US07301815B2

公开(公告)日：2007-11-27

申请号：US11180659

申请日：2005-07-14

申请人： Hideaki Kurata ,  Yoshihiro Ikeda ,  Masahiro Shimizu ,  Kenji Kozakai ,  Satoshi Noda

发明人： Hideaki Kurata ,  Yoshihiro Ikeda ,  Masahiro Shimizu ,  Kenji Kozakai ,  Satoshi Noda

IPC分类号： G11C11/34

CPC分类号： G11C8/14

摘要： The present invention provides a semiconductor memory device capable of preventing a defect caused by falling of a word line and deterioration in patterning precision due to disturbance of the pitch of word lines at an end of a memory block. Plural dummy word lines are disposed at an end of a memory block and a word driver is mounted for the dummy word line to control the threshold voltage of a dummy memory cell formed below the dummy word line. Also at the time of operating a memory area for storing data from the outside, a bias is applied to the dummy word line. The invention can prevent a defect caused by falling of a word line and deterioration in patterning precision due to disturbance of the pitches of word lines at an end of a memory block, and realize high yield and reliable operation.

摘要翻译： 本发明提供了一种半导体存储器件，其能够防止由于字线下降引起的缺陷以及由于在存储器块的末端处的字线的间距的干扰而引起的图案精度的劣化。 多个虚拟字线设置在存储器块的一端，并且为虚拟字线安装字驱动器以控制形成在虚拟字线下方的虚拟存储器单元的阈值电压。 此外，在操作用于存储来自外部的数据的存储区域时，偏置被施加到虚拟字线。 本发明可以防止由于字线下降引起的缺陷和由于记忆块末端的字线的间距的干扰导致的图案精度的劣化，并且实现了高产率和可靠的操作。

公开(公告)号：US20070257306A1

公开(公告)日：2007-11-08

申请号：US11808228

申请日：2007-06-07

申请人： Tomoyuki Ishii ,  Taro Osabe ,  Hideaki Kurata ,  Takeshi Sakata

发明人： Tomoyuki Ishii ,  Taro Osabe ,  Hideaki Kurata ,  Takeshi Sakata

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  B82Y10/00 ,  G11C11/5621 ,  G11C11/5671 ,  G11C16/0433 ,  G11C16/0458 ,  G11C16/0475 ,  G11C16/0491 ,  G11C2216/06 ,  H01L27/115 ,  H01L27/11521

摘要： Disclosed is a non-volatile semiconductor memory device that uses a inversion layer provided on a semiconductor substrate as a data line. The memory device can reduce variation of characteristics among memory cells and can reduce bit cost. A plurality of assist gates are formed in the upper part of a p-type well through a gate oxide film. In the upper part of an interlayer insulator that covers those assist gates are formed word lines that are used as control electrodes. The width of those word lines is, for example, 0.1 μm, and each word line is separated from its adjacent word lines by a side wall spacer that is a silicon oxide film having a thickness of about 20 nm.

公开(公告)号：US07238570B2

公开(公告)日：2007-07-03

申请号：US11271739

申请日：2005-11-14

申请人： Tomoyuki Ishii ,  Taro Osabe ,  Hideaki Kurata ,  Takeshi Sakata

发明人： Tomoyuki Ishii ,  Taro Osabe ,  Hideaki Kurata ,  Takeshi Sakata

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  B82Y10/00 ,  G11C11/5621 ,  G11C11/5671 ,  G11C16/0433 ,  G11C16/0458 ,  G11C16/0475 ,  G11C16/0491 ,  G11C2216/06 ,  H01L27/115 ,  H01L27/11521

摘要： Disclosed is a non-volatile semiconductor memory device that uses a inversion layer provided on a semiconductor substrate as a data line. The memory device can reduce variation of characteristics among memory cells and can reduce bit cost. A plurality of assist gates are formed in the upper part of a p-type well through a gate oxide film. In the upper part of an interlayer insulator that covers those assist gates are formed word lines that are used as control electrodes. The width of those word lines is, for example, 0.1 μm, and each word line is separated from its adjacent word lines by a side wall spacer that is a silicon oxide film having a thickness of about 20 nm.

摘要翻译： 公开了使用设置在半导体衬底上的反转层作为数据线的非易失性半导体存储器件。 存储器件可以减少存储器单元之间的特性变化并且可以降低位成本。 多个辅助栅极通过栅极氧化膜形成在p型阱的上部。 在覆盖这些辅助栅极的层间绝缘体的上部形成用作控制电极的字线。 这些字线的宽度例如为0.1μm，并且每个字线通过作为厚度为约20nm的氧化硅膜的侧壁间隔物与其相邻字线分开。