公开(公告)号：US20180167844A1

公开(公告)日：2018-06-14

申请号：US15656854

申请日：2017-07-21

Applicant: Redpine Signals, Inc.

Inventor： Govardhan MATTELA

IPC: H04W28/04 ,  H04W4/00 ,  H04W4/22 ,  H04W4/08 ,  H04W4/04 ,  H04W24/08

CPC classification number: H04L1/188 ,  H04L1/08 ,  H04L1/189 ,  H04L61/6022 ,  H04L2001/0093 ,  H04W4/026 ,  H04W4/029 ,  H04W4/08 ,  H04W4/46 ,  H04W4/90 ,  H04W84/18

Abstract: A system for transmission of incident information includes maintaining a table of RSSI values for a plurality of stations. When an incident is detected, the system first sends a broadcast packet with incident information, and next sends a unicast packet to any station below a particular RSSI threshold until the unicast packet is acknowledged or a retransmission interval passes.

公开(公告)号：US09703899B1

公开(公告)日：2017-07-11

申请号：US14829530

申请日：2015-08-18

Applicant: Redpine Signals, Inc.

Inventor： Venkat Mattela ,  Narasimhan Venkatesh ,  Dhiraj Sogani ,  Apurva Peri

IPC: G06F17/50 ,  H05K3/00

CPC classification number: G06F17/50 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/02 ,  H05K3/0005

Abstract: A product synthesizer has a core CPU, power distribution, and a plurality of selectable interfaces, each interface having an associated schematic symbol, PCB symbol, mechanical model, power dissipation, and power requirement. A set of constraints identifies performance metrics including low power, high performance, battery or mains power, battery life, and other constraints. The product synthesizer receives as inputs the interfaces and constraints, and generates as outputs a schematic diagram, a bill of materials, a routed printed circuit board, and a solid model of an enclosure, all of which satisfy the constraints and include the identified interfaces.

公开(公告)号：US09520646B1

公开(公告)日：2016-12-13

申请号：US14311261

申请日：2014-06-21

Applicant: Deepu Vasudevan Nair ,  Varun Ramchandani ,  Suresh Kumar Vagvala ,  Partha Sarathy Murali

Inventor： Deepu Vasudevan Nair ,  Varun Ramchandani ,  Suresh Kumar Vagvala ,  Partha Sarathy Murali

IPC: H01Q5/00 ,  H01Q1/48 ,  H01Q9/04 ,  H01Q1/24

CPC classification number: H01Q5/0027 ,  H01Q1/243 ,  H01Q1/38 ,  H01Q1/48 ,  H01Q5/392 ,  H01Q9/045 ,  H01Q9/42

Abstract: A printed circuit antenna has a feedline region and a radiating structure region. The feedline region is formed of conductors on an upper plane, the conductors including a feedline which is edge coupled to a left ground structure and a right ground structure, all of which are above a ground plane. High-band RF is coupled from the RF feedline to a HB-U radiating structure including a first segment and a second segment perpendicular to the first segment, and also an HB-L radiating structure including a first segment coupled to a third segment through an air gap. Low-band RF is coupled across a gap from the first segment to a LB radiating structure having a third segment, a fourth segment, a fifth segment, a sixth segment, a seventh segment, an eighth segment, and a ninth segment with a terminus coupled to the left ground structure.

Abstract translation: 印刷电路天线具有馈线区域和辐射结构区域。 馈线区域由上平面上的导体形成，导体包括与左接地结构边缘耦合的馈线和右接地结构，所有这些都在接地平面之上。 高频RF从RF馈线耦合到包括垂直于第一段的第一段和第二段的HB-U辐射结构，还包括一个HB-L辐射结构，其包括通过一个第二段耦合到第三段的第一段 气隙。 低频RF耦合跨越从第一段到具有第三段，第四段，第五段，第六段，第七段，第八段和第九段的具有终点的第一段的间隔 耦合到左地面结构。

公开(公告)号：US08332451B2

公开(公告)日：2012-12-11

申请号：US12324835

申请日：2008-11-27

Applicant: Phanimithra Gangalakurti ,  Karthik Vaidyanathan ,  Partha Sarathy Murali ,  InduSheknar Ayyalasomayajula

Inventor： Phanimithra Gangalakurti ,  Karthik Vaidyanathan ,  Partha Sarathy Murali ,  InduSheknar Ayyalasomayajula

IPC: G06F7/38 ,  G06F17/14

CPC classification number: G06F7/5446

Abstract: A CORDIC processor has a plurality of stages, each of the stages having a X input, Y input, a sign input, a sign output, an X output, a Y output, a mode control input having a ROTATE or VECTOR value, and a stage number k input, each CORDIC stage having a first shift generating an output by shifting the Y input k times, a second shift generating an output by shifting X input k times, a multiplexer having an output coupled to the sign input when the mode control input is ROTATE and to the sign of the Y input when the mode input is VECTOR, a first multiplier forming the product of the first shift output and the multiplexer output, a second multiplier forming the product of the second shift output and an inverted the multiplexer output, a first adder forming the X output from the sum of the first multiplier output and the X input, and a second adder forming the Y output from the sum of the second multiplier output and the Y input.

Abstract translation: CORDIC处理器具有多个级，每个级具有X输入，Y输入，符号输入，符号输出，X输出，Y输出，具有ROTATE或VECTOR值的模式控制输入，以及 每个CORDIC级具有通过移位Y输入k次而产生输出的第一移位，通过移位X个输入k次来产生输出的第二移位;当模式控制时，具有耦合到符号输入的输出的多路复用器 当模式输入为VECTOR时，输入为ROTATE和Y输入的符号，形成第一移位输出和多路复用器输出的积的第一乘法器，形成第二移位输出和反相多路复用器的乘积的第二乘法器 输出，从第一乘法器输出和X输入的和形成X输出的第一加法器和从第二乘法器输出和Y输入的和形成Y输出的第二加法器。

公开(公告)号：US08245063B2

公开(公告)日：2012-08-14

申请号：US12144853

申请日：2008-06-24

Applicant: Subba Reddy Kallam

Inventor： Subba Reddy Kallam

IPC: G06F1/00 ,  G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/324 ,  Y02D10/126

Abstract: A clock selector operative on two clocks operating on different domains and responsive to a SELECT input provides a transition from a first clock to a second clock, and from a second clock to a first clock with a dead zone therebetween. The delay is provided by a doublet register having a first register coupled to a second register, the two registers operative on one of the clock domains. Additionally, a clock selector is operative on two clocks which are each accompanied by a clock availability signal where the state machine provides a variety of states to create a dead zone between selections, and to bring the state machine to a known state until a clock signal is again available.

Abstract translation: 在两个时钟操作的时钟选择器，其操作在不同的域上并且响应于SELECT输入提供从第一时钟到第二时钟的转换，并且从第二时钟到第一时钟之间具有死区。 延迟由具有耦合到第二寄存器的第一寄存器的双寄存器提供，两个寄存器在时钟域之一上操作。 此外，时钟选择器在两个时钟上工作，每个时钟都伴随着时钟可用性信号，其中状态机提供各种状态以在选择之间创建死区，并且使状态机进入已知状态，直到时钟信号 再次可用

公开(公告)号：US08165251B2

公开(公告)日：2012-04-24

申请号：US12197230

申请日：2008-08-23

Applicant: Prem Kiran Nerella ,  Karthik Vaidyanathan ,  Partha Sarathy Murali

Inventor： Prem Kiran Nerella ,  Karthik Vaidyanathan ,  Partha Sarathy Murali

IPC: H04B1/10

CPC classification number: H04L27/2647 ,  H04L27/2626

Abstract: A filter for receiver and operative on a stream of OFDM symbols has a symbol timing identifier which indicates the time interval for each symbol and also indicates a non-truncation interval and a truncation interval of the stream of symbols. The stream of OFDM symbols is applied to an infinite impulse response (IIR) filter with a reset input for resetting internal registers such that during the non-truncation interval, the reset input is not asserted, and during the truncation interval of the stream of OFDM symbols, the reset input is asserted during the intervals between symbols, as identified by the symbol timing identifier.A transmit filter for a stream of OFDM symbols, each symbol being separated into a first Tg interval, a second Tg interval, a symbol interval, and a final Tg interval, the filter has a stream modifier which discards the first Tg interval, accepts said second Tg interval, accepts the symbol interval and discards said final Tg interval, presenting to an infinite impulse response filter, in sequence, the second Tg interval, the symbol interval and the second Tg interval.

Abstract translation: 用于接收机并在OFDM符号流上操作的滤波器具有指示每个符号的时间间隔的符号定时标识符，并且还指示符号流的非截断间隔和截断间隔。 OFDM符号流被应用于具有用于复位内部寄存器的复位输入的无限脉冲响应（IIR）滤波器，使得在非截断间隔期间，复位输入不被断言，并且在OFDM的流的截断间隔期间 在由符号定时标识符识别的符号之间的间隔期间，复位输入被断言。 一种用于OFDM符号流的发射滤波器，每个符号被分成第一Tg间隔，第二Tg间隔，符号间隔和最终Tg间隔，滤波器具有丢弃第一Tg间隔的流修改器，接受所述 第二Tg间隔接受符号间隔并丢弃所述最终Tg间隔，依次呈现无限脉冲响应滤波器，第二Tg间隔，符号间隔和第二Tg间隔。

公开(公告)号：US08161205B1

公开(公告)日：2012-04-17

申请号：US11803809

申请日：2007-05-16

Applicant: Narasimhan Venkatesh ,  Satya Rao

Inventor： Narasimhan Venkatesh ,  Satya Rao

IPC: G06F13/00 ,  G06F13/28

CPC classification number: G06F13/128

Abstract: A reduced complexity maximum likelihood decoder receives a stream of received symbols Y accompanied by a channel estimate matrix H. A variable transformation part includes a first part which converts Y and H into Z and R by computing a matrix R having at least one non-zero element in a row, such that the product of R and Q produces matrix H. A second variable transformation part column-swaps matrix H to form H′, thereafter generating Q′ and R′ subject to the same constraints as was described for Q and R. Transformed variables Z and Z′ are formed by multiplying Y by QH and Q′H, respectively. A reduced complexity maximum likelihood decoder has a first part which accepts Z and R and forms a first metric table having entries of all possible x2 accompanied by estimates of x1 derived from x2 and Z, and also including a distance metric. The reduced complexity maximum likelihood decoder has a second part which accepts Z′ and R′ and forms a second metric table having entries of all possible x1 accompanied by estimates of x2 derived from x1 and Z′, and also including a distance metric. A hard decision is made by finding the minimum distance metric of the combined entries of the first and second table. Soft values are also computed using this table.

Abstract translation: 减少的复杂度最大似然解码器接收伴随有信道估计矩阵H的接收符号Y的流。可变变换部分包括通过计算具有至少一个非零的矩阵R将Y和H转换为Z和R的第一部分 使得R和Q的乘积产生矩阵H.第二可变变换部分将矩阵H交替以形成H'，之后产生与描述为Q和Q相同约束的Q'和R' 变换变量Z和Z'分别通过将Y乘以QH和Q'H来形成。 降低的复杂度最大似然解码器具有接受Z和R的第一部分，并形成具有所有可能x2的条目的第一度量表，伴随着从x2和Z导出的x1的估计，并且还包括距离度量。 降低的复杂度最大似然解码器具有接受Z'和R'的第二部分，并且形成具有所有可能的条目的第二度量表，伴随着从x1和Z'导出的x2的估计，并且还包括距离度量。 通过找到第一和第二表的组合条目的最小距离度量来做出硬决定。 软值也使用此表计算。

公开(公告)号：US08160190B2

公开(公告)日：2012-04-17

申请号：US12197229

申请日：2008-08-22

Applicant: Prem Kiran Nerella ,  Karthik Vaidyanathan ,  Partha Sarathy Murali

Inventor： Prem Kiran Nerella ,  Karthik Vaidyanathan ,  Partha Sarathy Murali

IPC: H04B1/10

CPC classification number: H04L27/2626 ,  H04L27/2647

Abstract: A receive filter for a stream of OFDM symbols has an infinite impulse response (IIR) filter which receives packets having a preamble part followed by a data part, the data part having a succession of cyclic prefixes followed by OFDM symbols. The packet is provided to the IIR filter, and the registers of the IIR filter are reset before or during each cyclic prefix. The IIR filter may be formed from registers which are coupled to return a value to a predecessor register, or as an array of registers, such as in a BIQUAD configuration, where the registers are reset by a shared reset signal.

Abstract translation: 用于OFDM符号流的接收滤波器具有无限脉冲响应（IIR）滤波器，其接收具有后继数据部分的前导码部分的分组，该数据部分具有随后是OFDM符号的一系列循环前缀。 该分组被提供给IIR滤波器，并且IIR滤波器的寄存器在每个循环前缀之前或期间被复位。 IIR滤波器可以由寄存器形成，寄存器被耦合以将值返回到前驱寄存器，或者作为诸如在BIQUAD配置中的寄存器阵列，其中寄存器被共享复位信号复位。

公开(公告)号：US08090035B2

公开(公告)日：2012-01-03

申请号：US12211301

申请日：2008-09-16

Applicant: Dharani Naga Sailaja Sankabathula ,  Partha Sarathy Murali ,  Logeshwaran Vijayan ,  Nagaraja Reddy Anakala

Inventor： Dharani Naga Sailaja Sankabathula ,  Partha Sarathy Murali ,  Logeshwaran Vijayan ,  Nagaraja Reddy Anakala

IPC: H04K1/10 ,  H04L27/28

CPC classification number: H03G3/3052 ,  H04L27/0006 ,  H04L27/2647

Abstract: An packet detection controller accepts an input from an AGC controller which indicates the presence of an increased signal energy and also completion of an AGC process and generates an output to suspend the AGC process. The packet detection controller also receives a plurality of IQ receiver streams and forms a single stream for use by a packet detector, which is controllable by an SNR_MODE indicating whether the signal to noise ratio is above or below a particular threshold, and a PD_RESET signal indicating that no packet detection should occur. The controller also receives a PACKET_DET signal indicating that packet detection is completed. The packet detection controller examines the incoming receiver streams and suspends AGC process if a packet detect is generated, or suspends the packet detector if an AGC process is required.

Abstract translation: 分组检测控制器接受来自AGC控制器的输入，其指示增加的信号能量的存在以及AGC处理的完成，并且产生用于暂停AGC过程的输出。 分组检测控制器还接收多个IQ接收机流并且形成单个流以供分组检测器使用，该分组检测器可以由指示信噪比是高于还是低于特定阈值的SNR_MODE控制，以及表示PD_RESET信号的PD_RESET信号 不会发生数据包检测。 控制器还接收一个指示分组检测完成的PACKET_DET信号。 如果产生分组检测，分组检测控制器检查输入的接收机流并暂停AGC处理，或者如果需要AGC过程则暂停分组检测器。

公开(公告)号：US08051222B2

公开(公告)日：2011-11-01

申请号：US12145514

申请日：2008-06-25

Applicant: Subba Reddy Kallam ,  Venkateswarlu Upputuri

Inventor： Subba Reddy Kallam ,  Venkateswarlu Upputuri

IPC: G06F3/00

CPC classification number: G06F13/28

Abstract: An apparatus and a process for transferring packet data includes receiving packets from a first interface such as a network interface and transferring data to a second interface such as an SD Bus interface such as SDIO using a protocol such as one described in SDCard.org. The SD Bus second interface operates as a slave device to a master device, and the packet transfer from first interface to second interface includes concatenating length fields and packet data fields from packets received on the first interface to form a superframe which is provided to the second interface at time of data transfer. The formation of each superframe includes starting a timer such that the superframe is transmitted to the second interface by asserting an interrupt on that interface when either the timer expires, the number of packet from the first interface exceeds a threshold, or the amount of data from the first interface exceeds a threshold.

Abstract translation: 用于传送分组数据的装置和过程包括从诸如网络接口的第一接口接收分组，并使用诸如SDCard.org中描述的协议将数据传送到诸如SDIO之类的SD总线接口的诸如SD总线接口的第二接口。 SD总线第二接口作为主设备的从设备工作，并且从第一接口到第二接口的分组传送包括从在第一接口上接收的分组连接长度字段和分组数据字段，以形成提供给第二接口的超帧 接口在数据传输时。 每个超帧的形成包括启动定时器，使得当定时器到期时，通过在该接口上断言该中断，从第一接口的分组数超过阈值或从该接口的数据量，将超帧发送到第二接口 第一个接口超过阈值。