公开(公告)号：US07539045B2

公开(公告)日：2009-05-26

申请号：US10536293

申请日：2003-11-06

申请人： Hans Marc Bert Boeve

发明人： Hans Marc Bert Boeve

IPC分类号： G11C11/02

CPC分类号： G11C11/1675 ,  G11C11/1659

摘要： Magnetic or magnetoresistive random access memories (MRAMs) are implemented in a variety of arrangements and methods. Using one such arrangement, a matrix is implemented with magnetoresistive memory cells logically organized in rows and columns, each memory cell including a magnetoresistive element. The matrix has a set of column lines, a column line being a continuous conductive strip which is magnetically coupled to the magnetoresistive element of each of the memory cells of a column, wherein each column line has a forward column line and a return column line arranged on opposite sides of the magnetoresistive element and offset from one another for forming a return path for current in that column line.

摘要翻译： 磁性或磁阻随机存取存储器（MRAM）以各种布置和方法实现。 使用一种这样的布置，矩阵由具有逻辑地组织在行和列中的磁阻存储器单元实现，每个存储单元包括磁阻元件。 矩阵具有一列列线，列线是连续导电条，其磁耦合到列的每个存储单元的磁阻元件，其中每个列线具有正列列线和返回列线布置 在磁阻元件的相对侧上并且彼此偏移以形成用于该列线中的电流的返回路径。

公开(公告)号：US07535069B2

公开(公告)日：2009-05-19

申请号：US11452741

申请日：2006-06-14

申请人： David W. Abraham ,  Stephen L. Brown ,  Stuart P. Parkin ,  Daniel Worledge

发明人： David W. Abraham ,  Stephen L. Brown ,  Stuart P. Parkin ,  Daniel Worledge

IPC分类号： H01L29/82 ,  G11C11/02

CPC分类号： G11C11/16

摘要： A semiconductor device formed between a wordline and a bitline comprises a growth layer, an antiferromagnetic layer formed on the growth layer, a pinned layer formed on the antiferromagnetic layer, a tunnel barrier layer formed on the pinned layer, and a free layer formed on the tunnel barrier. The wordline and bitline are arranged substantially orthogonal to one another. The growth layer, in turn, comprises tantalum and has a thickness greater than about 75 Angstroms. Moreover, the pinned layer comprises one or more pinned ferromagnetic sublayers. The tunnel barrier comprises magnesium oxide. Finally, the free layer comprises two or more free ferromagnetic sublayers, each free ferromagnetic sublayer having a magnetic anisotropy axis that is oriented about 45 degrees from the wordline and bitline. The semiconductor device may comprise, for example, a magnetic tunnel junction for use in magnetoresistive random access memory (MRAM) circuitry.

摘要翻译： 形成在字线和位线之间的半导体器件包括生长层，形成在生长层上的反铁磁层，形成在反铁磁性层上的被钉扎层，形成在钉扎层上的隧道势垒层，以及形成在该引线层上的自由层 隧道屏障。 字线和位线彼此基本正交地布置。 生长层又包括钽，其厚度大于约75埃。 此外，被钉扎层包括一个或多个钉扎铁磁子层。 隧道势垒包括氧化镁。 最后，自由层包括两个或更多个自由铁磁子层，每个自由铁磁子层具有与字线和位线约45度的磁各向异性轴。 半导体器件可以包括例如用于磁阻随机存取存储器（MRAM）电路中的磁性隧道结。

公开(公告)号：US20090109739A1

公开(公告)日：2009-04-30

申请号：US12255624

申请日：2008-10-21

申请人： Rajiv Yadav RANJAN ,  Roger Klaus Malmhall ,  Parviz Keshtbod

发明人： Rajiv Yadav RANJAN ,  Roger Klaus Malmhall ,  Parviz Keshtbod

IPC分类号： G11C11/02

CPC分类号： H01L27/222 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/5607 ,  G11C19/0808 ,  H01L43/08

摘要： A multi-state low-current-switching magnetic memory element (magnetic memory element) comprising a free layer, two stacks, and a magnetic tunneling junction is disclosed. The stacks and magnetic tunneling junction are disposed upon surfaces of the free layer, with the magnetic tunneling junction located between the stacks. The stacks pin magnetic domains within the free layer, creating a free layer domain wall. A current passed from stack to stack pushes the domain wall, repositioning the domain wall within the free layer. The position of the domain wall relative to the magnetic tunnel junction corresponds to a unique resistance value, and passing current from a stack to the magnetic tunnel junction reads the magnetic memory element's resistance. Thus, unique memory states may be achieved by moving the domain wall.

摘要翻译： 公开了一种包括自由层，两个堆叠和磁性隧道结的多状态低电流切换磁存储元件（磁存储元件）。 堆叠和磁性隧道结设置在自由层的表面上，磁性隧道结位于堆叠之间。 堆叠在自由层内引导磁畴，产生自由层畴壁。 从堆栈传递到堆栈的电流推动域壁，重新定位自由层内的域壁。 畴壁相对于磁性隧道结的位置对应于唯一的电阻值，并且将电流从堆叠传递到磁性隧道结读取磁存储元件的电阻。 因此，可以通过移动域壁来实现唯一的记忆状态。

公开(公告)号：US20090097298A1

公开(公告)日：2009-04-16

申请号：US11873289

申请日：2007-10-16

申请人： Ulrich Klostermann

发明人： Ulrich Klostermann

IPC分类号： G11C5/06 ,  G11C11/02

CPC分类号： G11C11/16 ,  G11C5/063 ,  G11C11/1675 ,  H01L27/224 ,  H01L27/228

摘要： According to one embodiment of the present invention, an integrated circuit includes an arrangement of memory cells. Each memory cell is connected to a programming current path used for programming the memory cell, and a sensing current path used for sensing the memory state of the memory cell. The programming current path and the sensing current path are at least partly separated from each other.

摘要翻译： 根据本发明的一个实施例，集成电路包括存储单元的布置。 每个存储单元连接到用于编程存储单元的编程电流路径，以及用于感测存储单元的存储状态的感测电流路径。 编程电流路径和感测电流路径至少部分地彼此分离。

公开(公告)号：US20090091969A1

公开(公告)日：2009-04-09

申请号：US12244036

申请日：2008-10-02

申请人： Yoshihiro UEDA

发明人： Yoshihiro UEDA

IPC分类号： G11C11/00 ,  G11C11/02 ,  G11C11/409

CPC分类号： G11C5/147 ,  G11C11/1675 ,  G11C11/1697 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2213/79

摘要： A resistance change memory includes a memory cell which is connected to a first node, and programmed from a first resistance state to a second resistance state, a first replica cell which is connected to a second node, generates a write voltage for programming from the first resistance state to the second resistance state, and is fixed in the first resistance state, and a first constant-current source connected to the second node, wherein when writing the second resistance state in the memory cell, a voltage of the first node is held equal to that of the second node.

摘要翻译： 电阻变化存储器包括连接到第一节点并被编程从第一电阻状态到第二电阻状态的存储单元，连接到第二节点的第一复制单元从第一节点产生用于编程的写入电压 电阻状态到第二电阻状态，并且被固定在第一电阻状态，以及连接到第二节点的第一恒流源，其中当将第二电阻状态写入存储单元时，保持第一节点的电压 等于第二个节点。

公开(公告)号：US20090073737A1

公开(公告)日：2009-03-19

申请号：US11856659

申请日：2007-09-17

申请人： Ulrich Klostermann ,  Rainer Leuschner

发明人： Ulrich Klostermann ,  Rainer Leuschner

IPC分类号： G11C7/02 ,  G11C11/02 ,  H01L21/00

CPC分类号： H01L27/222 ,  G11C11/161 ,  H01L43/08

摘要： Embodiments of the invention relate generally to integrated circuits, to methods for manufacturing an integrating circuit, and to memory modules. In an embodiment of the invention, an integrated circuit is provided having a memory cell. The memory cell may include a first magnetic layer structure, a tunnel barrier layer structure disposed above the first magnetic layer structure, a second magnetic layer structure disposed above the tunnel barrier layer structure, and at least one sacrificial material layer to suppress electrochemical corrosion of the first magnetic layer structure or the second magnetic layer structure.

摘要翻译： 本发明的实施例一般涉及集成电路，用于制造集成电路的方法以及存储器模块。 在本发明的实施例中，提供了具有存储单元的集成电路。 存储单元可以包括第一磁性层结构，设置在第一磁性层结构之上的隧道阻挡层结构，设置在隧道势垒层结构之上的第二磁性层结构，以及至少一个牺牲材料层，以抑制 第一磁性层结构或第二磁性层结构。

公开(公告)号：US20080273377A1

公开(公告)日：2008-11-06

申请号：US12171893

申请日：2008-07-11

申请人： Won-Cheol Jeong ,  Jae-Hyun Park

发明人： Won-Cheol Jeong ,  Jae-Hyun Park

IPC分类号： G11C11/02 ,  G11C7/00

CPC分类号： H01L43/08 ,  G11C11/16 ,  H01L27/222

摘要： A magnetic random access memory (MRAM) device may include a substrate, a first magnetic layer on the substrate, and a digit line on the first magnetic layer. A magnetic tunnel junction structure may be provided adjacent the digit line, and a bit line may be provided on the magnetic tunnel junction structure such that the magnetic tunnel junction structure is between the bit line and the digit line. In addition, a second magnetic layer may be provided on the bit line.

摘要翻译： 磁性随机存取存储器（MRAM）器件可以包括衬底，衬底上的第一磁性层和第一磁性层上的数字线。 可以在数字线附近提供磁性隧道结结构，并且可以在磁性隧道结结构上提供位线，使得磁性隧道结结构位于位线和数字线之间。 此外，可以在位线上设置第二磁性层。

公开(公告)号：US20080062750A1

公开(公告)日：2008-03-13

申请号：US11935662

申请日：2007-11-06

申请人： Won-Cheol Jeong ,  Jae-Hyun Park

发明人： Won-Cheol Jeong ,  Jae-Hyun Park

IPC分类号： G11C11/02

CPC分类号： G11C11/15

摘要： A magnetic random access memory device may include a memory cell access transistor on a substrate, a bit line spaced apart from the substrate, and a magnetic tunnel junction structure electrically coupled between the bit line and the memory cell access transistor. At least one magnet may be positioned adjacent a sidewall of the magnetic tunnel junction structure and may be configured to provide a magnetic field through the magnetic tunnel junction structure. Related methods of operating magnetic random access memory devices are also discussed.

摘要翻译： 磁性随机存取存储器件可以包括衬底上的存储单元存取晶体管，与衬底间隔开的位线以及电耦合在位线和存储单元存取晶体管之间的磁性隧道结结构。 至少一个磁体可以邻近磁性隧道结结构的侧壁定位，并且可以被配置为通过磁性隧道结结构提供磁场。 还讨论了操作磁随机存取存储器件的相关方法。

公开(公告)号：US20080043518A1

公开(公告)日：2008-02-21

申请号：US11813949

申请日：2005-12-29

申请人： Hans Schumacher

发明人： Hans Schumacher

IPC分类号： G11C11/02

CPC分类号： G11C11/16 ,  Y10S977/935

摘要： Method of magnetization reversal of the magnetization (M) of at least one first magnetic memory element of an array of magnetic memory elements comprising the steps of: applying a first magnetic field pulse to a first set of magnetic memory elements, and applying a second magnetic field pulse to a second set of magnetic memory elements, such that during the application of the first and second magnetic field pulse the magnetization (M) of said first magnetic memory element which is to be reversed upon the field pulse decay performs approximately an odd number of a half precessional turns, wherein the magnetization (M) of at least one second magnetic memory element which is not to be reversed upon the field pulse decay performs approximately a number of full precessional turns. The underlying concept of the invention is to improve the bit addressing in an array of magnetic memory cells by reducing the ringing of the magnetization of the free layer of the magnetic cells which are not selected for reversal but which are nevertheless subject to the application of a magnetic field pulse. This can be achieved by applying a field pulse to these cells which induces approximately a full precessional turn of the magnetization of the free layer of the cells. After the full precessional turn the magnetization is oriented very near the initial orientation along the easy application of the half select field pulse is reduced.

摘要翻译： 磁存储元件阵列的至少一个第一磁存储元件的磁化（M）的磁化反转方法包括以下步骤：将第一磁场脉冲施加到第一组磁存储元件，以及施加第二磁性 场脉冲到第二组磁存储元件，使得在施加第一和第二磁场脉冲期间，所述第一磁存储元件的磁场（M）在场脉冲衰减时被反转，执行大约奇数 其中在场脉冲衰减时不被反转的至少一个第二磁存储元件的磁化强度（M）执行大约一定数量的全进位匝数。 本发明的基本概念是通过减少不被选择用于反转的磁性单元的自由层的磁化的振荡来改善磁存储单元的阵列中的位寻址，但仍然需要应用 磁场脉冲。 这可以通过对这些单元施加场脉冲来实现，这些单元引起单元自由层的磁化的大致完全转动。 在完全进动转弯之后，磁化方向非常接近初始取向，沿着半选择场脉冲的容易应用减小。

公开(公告)号：US06980466B2

公开(公告)日：2005-12-27

申请号：US10758658

申请日：2004-01-15

申请人： Fredrick A. Perner ,  Manish Sharma

发明人： Fredrick A. Perner ,  Manish Sharma

IPC分类号： H01L27/105 ,  G11C11/15 ,  H01L21/8246 ,  H01L43/08 ,  G11C11/02

CPC分类号： G11C11/15

摘要： This invention provides a soft-reference four conductor magnetic memory storage device. In a particular embodiment, there are a plurality of parallel electrically conductive first sense conductors and a plurality of parallel electrically conductive second sense conductors. The first and second sense conductors may provide a cross point array or a series connected array. Soft-reference magnetic memory cells are provided in electrical contact with and located and at each intersection. In addition there are a plurality of parallel electrically conductive write rows substantially proximate to and electrically isolated from the first sense conductors. A plurality of parallel electrically conductive write columns transverse to the write rows, substantially proximate to and electrically isolated from the second sense conductors, forming a write cross point array with a plurality of intersections, is also provided. Sense magnetic fields generated by at least one conductor orient the soft-reference layer but do not alter the data stored within the cell. An associated method of use is also provided.