公开(公告)号：US20190068983A1

公开(公告)日：2019-02-28

申请号：US15686892

申请日：2017-08-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Stephen Mark Ryan ,  Darren Rae Di Cera

IPC: H04N19/196 ,  H04N19/105 ,  H04N19/159 ,  H04N19/172 ,  H04N19/597 ,  H04N19/164

Abstract: Systems, apparatuses, and methods for sending hybrid frames as part of an encoded video stream are disclosed. A system includes a transmitter and a receiver communicating wirelessly. The transmitter partitions a first frame of a video stream into a plurality of portions and sends the plurality of portions to the receiver. The transmitter records which portions of the first frame which were not acknowledged by the receiver. Next, the transmitter generates one or more first portions of a hybrid frame based only on data from a second frame of the video stream and the transmitter generates one or more second portions of the hybrid frame based on a comparison of data from the second frame to data of the first frame. The one or more first portions of the hybrid frame correspond to portions of the first frame which were not acknowledged by the receiver.

公开(公告)号：US20190068926A1

公开(公告)日：2019-02-28

申请号：US15686927

申请日：2017-08-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Ngoc Vinh Vu ,  David Robert Stark, JR. ,  Carson Ryley Reece Green

IPC: H04N7/20 ,  H04L29/06 ,  H01Q3/00

Abstract: Systems, apparatuses, and methods for scheduling beamforming training during vertical blanking intervals (VBIs) are disclosed. A system includes a transmitter sending a video stream over a wireless link to a receiver. The wireless link between the transmitter and the receiver has capacity characteristics that fluctuate with variations in the environment. To combat the fluctuating capacity characteristics of the link, the transmitter and the receiver perform periodic beamforming training procedures to determine whether to adjust the beamforming characteristics of their respective antennas. To avoid interfering with the video data being sent, the system waits until a VBI to perform a beamforming training procedure. If the beamforming training procedure cannot be completed in a single VBI, then multiple VBIs can be used for performing separate portions of the beamforming training procedure. In one embodiment, the system can perform a beamforming training procedure every N VBIs, where N is a positive integer.

公开(公告)号：US20190066371A1

公开(公告)日：2019-02-28

申请号：US15687421

申请日：2017-08-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Skyler Jonathon Saleh ,  Christopher J. Brennan ,  Andrew S. Pomianowski ,  Ruijin Wu

IPC: G06T15/80 ,  G06T15/40 ,  G06T15/00 ,  G06T11/40

CPC classification number: G06T15/80 ,  G06T11/40 ,  G06T15/005 ,  G06T15/405

Abstract: A technique for performing rasterization and pixel shading with decoupled resolution is provided herein. The technique involves performing rasterization as normal to generate fine rasterization data and a set of (fine) quads. The quads are accumulated into a tile buffer and coarse quads are generated from the quads in the tile buffer based on a shading rate. The shading rate determines how many pixels of the fine quads are combined to generate coarse pixels of the coarse quads. Combination of fine pixels involves generating a single coarse pixel for each such fine pixel to be combined. The positions of the coarse pixels of the coarse quads are set based on the positions of the corresponding fine pixels. The coarse quads are shaded normally and the resulting shaded coarse quads are modified based on the fine rasterization data to generate shaded fine quads.

公开(公告)号：US10210912B2

公开(公告)日：2019-02-19

申请号：US15618349

申请日：2017-06-09

Applicant: Advanced Micro Devices, Inc.

Inventor： Wei Huang

IPC: G11C7/04 ,  H01L27/108 ,  H01L23/38 ,  H01L35/32 ,  H01L27/16

Abstract: Managing temperature of a semiconductor device having a temperature inverted processor core and stacked memory by operation of an integrated thermoelectric cooler. The thermoelectric cooler is operated to pump heat from a stacked memory device that requires a cool operating temperature to a temperature inverted processor core that maintains a higher operating temperature until threshold operating temperatures are achieved.

公开(公告)号：US20190051363A1

公开(公告)日：2019-02-14

申请号：US15857887

申请日：2017-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Steven Raasch ,  Greg Sadowski ,  David A. Roberts

IPC: G11C16/34 ,  G06F12/02 ,  G06F3/06

Abstract: Exemplary embodiments provide wear spreading among die regions (i.e., one or more circuits) in an integrated circuit or among dies by using operating condition data in addition to or instead of environmental data such as temperature data, from each of a plurality of die regions. Control logic produces a cumulative amount of time each of the plurality of die regions has spent at an operating condition based on operating condition data wherein the operating condition data is based on at least one of the following operating characteristics: frequency of operation of the plurality of die regions, an operating voltage of the plurality of die regions, an activity level of the plurality of die regions, a timing margin of the plurality of die regions, and a number of detected faults of the plurality of die regions. The method and apparatus spreads wear among the plurality of same type of die regions by controlling task execution among the plurality of die regions using the die wear-out data.

公开(公告)号：US10198789B2

公开(公告)日：2019-02-05

申请号：US15377998

申请日：2016-12-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Daniel Schneider ,  Fataneh Ghodrat

IPC: G06T1/60 ,  G06F12/0815 ,  G06F12/0877 ,  G06F15/80 ,  G06T15/00 ,  G06T1/20

Abstract: Techniques for allowing cache access returns out of order are disclosed. A return ordering queue exists for each of several cache access types and stores outstanding cache accesses in the order in which those accesses were made. When a cache access request for a particular type is at the head of the return ordering queue for that type and the cache access is available for return to the wavefront that made that access, the cache system returns the cache access to the wavefront. Thus, cache accesses can be returned out of order with respect to cache accesses of different types. Allowing out-of-order returns can help to improve latency, for example in the situation where a relatively low-latency access type (e.g., a read) is issued after a relatively high-latency access type (e.g., a texture sampler operation).

公开(公告)号：US10198259B2

公开(公告)日：2019-02-05

申请号：US15191374

申请日：2016-06-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Robert A. Gottlieb ,  Christopher L. Reeve ,  Michael John Bedy

IPC: G06F9/30 ,  G06F15/80

Abstract: A method and apparatus for scheduling instructions of a shader program for a graphics processing unit (GPU) with a fixed number of registers. The method and apparatus include computing, via a processing unit (PU), a liveness-based register usage across all basic blocks in the shader program, computing, via the PU, the range of numbers of waves of a plurality of registers for the shader program, assessing the impact of available post-register allocation optimizations, computing, via the PU, the scoring data based on number of waves of the plurality of registers, and computing, via the PU, the number of waves for execution for the plurality of registers.

公开(公告)号：US10185604B2

公开(公告)日：2019-01-22

申请号：US14529299

申请日：2014-10-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Winthrop Wu

IPC: G06F9/50 ,  G06F9/54

Abstract: Methods and apparatus of interleaving two or more workloads are presented herein. The methods and apparatus may comprise a schedule controller and a coprocessor. The schedule controller is operative to utilize the first storage unit to manage context stored therein that allows for the coprocessor to interleave the two or more workloads that can be directly supported by the first storage unit. The coprocessor includes a dedicated first storage unit and an engine.

公开(公告)号：US20190018800A1

公开(公告)日：2019-01-17

申请号：US15650252

申请日：2017-07-14

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan JAYASENA ,  Brandon K. POTTER ,  Andrew G. KEGEL

IPC: G06F12/14 ,  G06F12/0875 ,  G06F9/48 ,  G06F9/455 ,  G06F9/50 ,  G06F12/10

Abstract: A host processor receives an address translation request from an accelerator, which may be trusted or un-trusted. The address translation request includes a virtual address in a virtual address space that is shared by the host processor and the accelerator. The host processor encrypts a physical address in a host memory indicated by the virtual address in response to the accelerator being permitted to access the physical address. The host processor then provides the encrypted physical address to the accelerator. The accelerator provides memory access requests including the encrypted physical address to the host processor, which decrypts the physical address and selectively accesses a location in the host memory indicated by the decrypted physical address depending upon whether the accelerator is permitted to access the location indicated by the decrypted physical address.

公开(公告)号：US20190005604A1

公开(公告)日：2019-01-03

申请号：US15639980

申请日：2017-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Anirudh R. ACHARYA ,  Michael MANTOR ,  Vineet GOEL ,  Swapnil SAKHARSHETE

IPC: G06T1/20 ,  G06T15/00 ,  G06T17/10

Abstract: A stage of a graphics pipeline in a graphics processing unit (GPU) detects an interrupt concurrently with the stage processing primitives in a first bin that represents a first portion of a first frame generated by a first application. The stage forwards a completed portion of the primitives to a subsequent stage of the graphics pipeline in response to the interrupt. The stage diverts a second bin that represents a second portion of the first frame from the stage to a memory in response to the interrupt. The stage processes primitives in a third bin that represents a portion of a second frame generated by a second application subsequent to diverting the second bin to the memory. The stage can then retrieve the second bin from the memory in response to the stage completing processing of the primitives in the third bin for additional processing.