公开(公告)号：US20210006256A1

公开(公告)日：2021-01-07

申请号：US16918940

申请日：2020-07-01

Applicant: STMicroelectronics SA ,  STMicroelectronics (Alps) SAS

Inventor： Stéphane Le Tual ,  David Duperray ,  Jean-Pierre Blanc

IPC: H03M1/12 ,  H01L29/78

Abstract: A sampling circuit includes a metal oxide semiconductor (MOS) transistor that includes a third metallization receiving a reference voltage between a first metallization coupled to a source region of the transistor and a second metallization coupled to a drain region of the transistor.

公开(公告)号：US20200373965A1

公开(公告)日：2020-11-26

申请号：US16878084

申请日：2020-05-19

Applicant: STMicroelectronics SA

Inventor： Mohammed TMIMI ,  Philippe GALY

IPC: H04B3/02 ,  H04L27/20

Abstract: Binary data is processed through a differential pre-encoder, which includes a simple modulo-2 addition. This step is used to cancel the propagation error that can be introduced by duo-binary modulation and to simplify demodulation. Next the duo-binary encoder introduces controlled Inter Symbol Interference between a previously sent bit and a present bit to compress the spectral density closer to the DC. Next a 60-GHz carrier is modulated and transmitted over differential transmission lines.

公开(公告)号：US20200350653A1

公开(公告)日：2020-11-05

申请号：US16764947

申请日：2017-11-21

Applicant: STMicroelectronics SA

Inventor： Vincent KNOPIK ,  Jeremie FOREST ,  Eric KERHERVE

IPC: H01P5/22 ,  H04B17/21 ,  H01L23/522 ,  H03H11/16

Abstract: A hybrid coupler operating in a power divider mode includes two inputs, two outputs, a capacitive module coupled between the inputs and the outputs or on each input and each output. The capacitive module has an adjustable capacitive value making it possible to adjust the central frequency. A calibration method includes: delivering a first reference signal having a first reference frequency on the first input of the hybrid coupler, measuring the peak value of a first signal delivered to the first output of the coupler and measuring the peak value of a second signal delivered to the second output of the coupler. The two peak values are compared and an adjustment of the capacitive value of the capacitive module is made until an equality of the peak values is obtained to within a tolerance.

公开(公告)号：US10804885B2

公开(公告)日：2020-10-13

申请号：US16654261

申请日：2019-10-16

Applicant: STMicroelectronics SA

Inventor： Sylvain Engels ,  Alain Aurand ,  Etienne Maurin

IPC: H03K3/00 ,  H03K3/356 ,  H01L27/02 ,  H03K3/3562 ,  H03K19/0948 ,  H01L23/528

Abstract: A standard cell layout for a data storage circuit includes a latch and an initialization circuit. Metallization levels over the standard cell layout support circuit interconnections. At least one metallization level is provided for metal programming of an initialization configuration of the data storage circuit. The at least one metallization level may have: a first wiring layout for interconnecting the initialization circuit to the latch for configuration programming of the data storage circuit as an initialization in reset device (assertion of an initialization signal causing the data storage circuit data output to be reset), or a second wiring layout for interconnecting the initialization circuit to the latch for configuration programming of the data storage circuit as an initialization in set device (assertion of the initialization signal causing the data storage circuit data output to be set).

公开(公告)号：US10771048B2

公开(公告)日：2020-09-08

申请号：US16747341

申请日：2020-01-20

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Capucine Lecat-Mathieu De Boissac ,  Fady Abouzeid ,  Gilles Gasiot ,  Philippe Roche ,  Victor Malherbe

IPC: H03K5/14 ,  H03K5/135 ,  H03K5/00

Abstract: A first circuit includes a first chain of identical stages defining first and second delay lines. A second circuit includes a second chain of identical stages defining third and fourth delay lines. The stages of the second chain are identical to the stages of the first chain. A third circuit selectively couples one of the third delay line, the fourth delay line, or a first input of the third circuit to an input of the first circuit.

公开(公告)号：US20200212927A1

公开(公告)日：2020-07-02

申请号：US16709391

申请日：2019-12-10

Applicant: STMicroelectronics SA ,  STMicroelectronics (Alps) SAS

Inventor： Stephane LE TUAL ,  Jean-Pierre BLANC ,  David DUPERRAY

IPC: H03M1/68 ,  H03M1/06

Abstract: An acquisition stage receives a digital input signal and generates therefrom a first digital signal and a second digital signal complementary thereto. First and second processing stages receive the first and second digital signals and generate therefrom first and second analog signals in time with first and second complementary clock signals. An output stage generates an internal clock signal equivalent to one of: the first clock signal phase shifted by a duration of a transient occurring during a period of the first clock signal, or the second clock signal phase shifted by a duration of a transient occurring during a period of the second clock signal. The output stage produces an analog output signal equal to the first analog signal when the internal clock signal is at a first logic level, and equal to the second analog signal when the internal clock signal is at a second logic level.

公开(公告)号：US10659034B2

公开(公告)日：2020-05-19

申请号：US16429544

申请日：2019-06-03

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Renan Lethiecq

IPC: H03K17/687 ,  H03K17/14 ,  H03K3/356 ,  H01L27/12

Abstract: An integrated electronic device includes a silicon-on-insulator (SOI) substrate. At least one MOS transistor is formed in and on the SOI substrate. The at least one MOS transistor has a gate region receiving a control voltage, a back gate receiving an adjustment voltage, a source/drain region having a resistive portion, a first terminal coupled to a first voltage (e.g., a reference voltage) and formed in the source/drain region and on a first side of the resistive portion, and a second terminal generating a voltage representative of a temperature of the integrated electronic device, the second terminal being formed in the source/drain region and on a second side of the resistive portion. Adjustment circuitry generates the adjustment voltage as having a value dependent on the control voltage and on the voltage generated by the second terminal.

公开(公告)号：US10607949B2

公开(公告)日：2020-03-31

申请号：US15607780

申请日：2017-05-30

Applicant: STMicroelectronics (Alps) SAS ,  STMicroelectronics SA

Inventor： Yves Mazoyer ,  Philippe Galy ,  Philippe Sirito-Olivier

IPC: H01L23/60 ,  H01L23/62 ,  H01L27/02

Abstract: Electrostatic discharge (ESD) protection is provided by a circuit including a resistor having a first terminal and a second terminal, a zener diode having a cathode terminal directly connected to said first terminal and an anode terminal directly connected to a third terminal, and a clamp diode having a cathode terminal directly connected to said second terminal and an anode terminal directly connected to said third terminal.

公开(公告)号：US10585143B2

公开(公告)日：2020-03-10

申请号：US16031960

申请日：2018-07-10

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Pascal Urard ,  Florian Cacho ,  Vincent Huard ,  Alok Kumar Tripathi

IPC: G01R31/3183 ,  G01R31/3185 ,  G01R31/3177 ,  G01R31/317 ,  G01R31/3181 ,  G06F17/50

Abstract: A flip flop includes a data input, a clock input, a test chain input, a test chain output, a monitoring circuit, and an alert transmission circuit. The monitoring circuit is adapted to generate an alert if the time between arrival of a data bit and a clock edge is less than a threshold. The alert transmission circuit is adapted to apply during a monitoring phase an alert level to the test chain output in the event of an alert generated by the monitoring circuit, and to apply the alert level to the test chain output when an alert level is received at the test chain input.

公开(公告)号：US20200006320A1

公开(公告)日：2020-01-02

申请号：US16454230

申请日：2019-06-27

Applicant: STMicroelectronics SA

Inventor： Thomas BEDECARRATS ,  Louise DE CONTI ,  Philippe GALY

IPC: H01L27/02

Abstract: A semiconductor substrate includes a doped region having an upper surface. The doped region may comprise a conduction terminal of a diode (such as cathode) or a transistor (such as a drain). A silicide layer is provided at the doped region. The silicide layer has an area that only partially covers an area of the upper surface of the doped region. The partial area coverage facilitates modulating the threshold voltage and/or leakage current of an integrated circuit device.