公开(公告)号：US20180246724A1

公开(公告)日：2018-08-30

申请号：US15442412

申请日：2017-02-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Mark Fowler ,  Brian D. Emberling

IPC: G06F9/30 ,  G06F12/0875

Abstract: Systems, apparatuses, and methods for maintaining separate pending load and store counters are disclosed herein. In one embodiment, a system includes at least one execution unit, a memory subsystem, and a pair of counters for each thread of execution. In one embodiment, the system implements a software based approach for managing dependencies between instructions. In one embodiment, the execution unit(s) maintains counters to support the software-based approach for managing dependencies between instructions. The execution unit(s) are configured to execute instructions that are used to manage the dependencies during run-time. In one embodiment, the execution unit(s) execute wait instructions to wait until a given counter is equal to a specified value before continuing to execute the instruction sequence.

公开(公告)号：US20180246700A1

公开(公告)日：2018-08-30

申请号：US15442144

申请日：2017-02-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Nicolai Hähnle

IPC: G06F7/52 ,  G06F7/487 ,  G06F17/17

CPC classification number: G06F7/52 ,  G06F7/487 ,  G06F7/535 ,  G06F17/17 ,  G06F2207/5355

Abstract: Systems, apparatuses, and methods for performing a division operation are disclosed. In one embodiment, a processor includes at least one arithmetic logic unit and a register file. In response to detecting a request to perform a division operation between a dividend and a divisor, the processor generates an initial approximation of the reciprocal of the divisor. Then, the processor converts the initial approximation of the reciprocal of the divisor into a fractional fixed point representation. The processor also introduces a small error into the initial approximation of the reciprocal of the divisor. Then, the processor implements one or more Newton-Raphson iterations for refining the approximation of the reciprocal and then multiplies the final reciprocal value by the dividend to generate the quotient.

公开(公告)号：US20180246657A1

公开(公告)日：2018-08-30

申请号：US15442511

申请日：2017-02-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Greg Sadowski

IPC: G06F3/06 ,  G06F17/30

CPC classification number: G06F16/1744 ,  G06F3/0608 ,  G06F3/064 ,  G06F3/068 ,  G06F2212/401 ,  H03M7/30 ,  H03M7/3077 ,  H03M7/3079 ,  H04L9/3247 ,  H04L63/123 ,  H04L63/126 ,  H04L69/04 ,  H04L2209/30

Abstract: Techniques for handling data compression in which metadata that indicates which portions of data are compressed are which portions of data are not compressed are disclosed. Segments of a buffer referred to as block groups store compressed blocks of data along with uncompressed blocks of data and hash blocks. If a block group includes a block that is a hash of another block in the block group, then the other block is considered to be compressed. If the block group does not include a block that is a hash of another block in the block group, then the blocks in the block group are uncompressed. The hash function to generate the hash is selected to prevent “collisions,” which occur when the data being stored in the buffer is such that it is possible for a hash block and an uncompressed block to be the same.

公开(公告)号：US20180239722A1

公开(公告)日：2018-08-23

申请号：US15958805

申请日：2018-04-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Greg Sadowski ,  Philip J. Rogers

IPC: G06F13/16

CPC classification number: G06F13/1673 ,  G06F13/1684 ,  Y02D10/14

Abstract: A method, computer program product, and system are provided for associating one or more memory buffers in a computing system with a plurality of memory channels. The method can include associating a first memory buffer to a first plurality of memory banks, where the first plurality of memory banks spans over a first set of one or more memory channels. Similarly, the method can include associating a second memory buffer to a second plurality of memory banks, where the second plurality of memory banks spans over a second set of one or more memory channels. The method can also include associating a first sequence identifier and a second sequence identifier with the first memory buffer and the second memory buffer, respectively. Further, the method can include accessing the first and second memory buffers based on the first and second sequence identifiers.

公开(公告)号：US10042576B2

公开(公告)日：2018-08-07

申请号：US15345639

申请日：2016-11-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Vydhyanathan Kalyanasundharam ,  Greggory D. Donley

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/0895

Abstract: A method and apparatus of compressing addresses for transmission includes receiving a transaction at a first device from a source that includes a memory address request for a memory location on a second device. It is determined if a first part of the memory address is stored in a cache located on the first device. If the first part of the memory address is not stored in the cache, the first part of the memory address is stored in the cache and the entire memory address and information relating to the storage of the first part is transmitted to the second device. If the first part of the memory address is stored in the cache, only a second part of the memory address and an identifier that indicates a way in which the first part of the address is stored in the cache is transmitted to the second device.

公开(公告)号：US10037267B2

公开(公告)日：2018-07-31

申请号：US15299990

申请日：2016-10-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander D. Breslow ,  Nuwan S. Jayasena ,  Dong Ping Zhang

IPC: G06F9/45 ,  G06F11/36 ,  G06F8/71 ,  G06F9/30

CPC classification number: G06F11/3688 ,  G06F8/71 ,  G06F9/30101 ,  G06F9/448 ,  G06F9/4843 ,  G06F9/5088

Abstract: Systems, apparatuses, and methods for migrating execution contexts are disclosed. A system includes a plurality of processing units and memory devices. The system is configured to execute any number of software applications. The system is configured to detect, within a first software application, a primitive for migrating at least a portion of the execution context of a source processing unit to a target processing unit, wherein the primitive includes one or more instructions. The execution context includes a plurality of registers. A first processing unit is configured to execute the one or more instructions of the primitive to cause a portion of an execution context of the first processing unit to be migrated to a second processing unit. In one embodiment, executing the primitive instruction(s) causes an instruction pointer value, with an optional offset value, to be sent to the second processing unit.

公开(公告)号：US10031947B2

公开(公告)日：2018-07-24

申请号：US14749063

申请日：2015-06-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Mayank Daga

IPC: G06F17/30

Abstract: A method and apparatus for performing a top-down Breadth-First Search (BFS) includes performing a first determination whether to convert to a bottom-up BFS. A second determination is performed whether to convert to the bottom-up BFS, based upon the first determination being positive. The bottom-up BFS is performed, based upon the first determination and the second determination being positive. A third determination is made whether to convert from the bottom-up BFS to the top-down BFS, based upon the third determination being positive.

公开(公告)号：US20180189190A1

公开(公告)日：2018-07-05

申请号：US15907593

申请日：2018-02-28

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Kaplan ,  Jeremy W. Powell ,  Thomas R. Woller

IPC: G06F12/1009 ,  G06F9/455

CPC classification number: G06F12/1009 ,  G06F9/45545 ,  G06F9/45558 ,  G06F12/1018 ,  G06F12/109 ,  G06F2009/45583 ,  G06F2212/1044 ,  G06F2212/151 ,  G06F2212/152 ,  G06F2212/657

Abstract: A computing device that handles address translations is described. The computing device includes a hardware table walker and a memory that stores a reverse map table and a plurality of pages of memory. The table walker is configured to use validated indicators in entries in the reverse map table to determine if page accesses are made to pages for which entries are validated. The table walker is further configured to use virtual machine permissions levels information in entries in the reverse map table determine if page accesses for specified operation types are permitted.

公开(公告)号：US10013240B2

公开(公告)日：2018-07-03

申请号：US15188304

申请日：2016-06-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Daniel I. Lowell

IPC: G06F9/45 ,  G06F8/30 ,  G06F11/16 ,  G06F8/41

CPC classification number: G06F8/30 ,  G06F8/41 ,  G06F8/454 ,  G06F11/1629 ,  G06F2201/805

Abstract: A first processing element is configured to execute a first thread and one or more second processing elements are configured to execute one or more second threads that are redundant to the first thread. The first thread and the one or more second threads are to selectively bypass one or more comparisons of results of operations performed by the first thread and the one or more second threads depending on whether an event trigger for the comparison has occurred a configurable number of times since a previous comparison of previously encoded values of the results. In some cases the comparison can be performed based on hashed (or encoded) values of the results of a current operation and one or more previous operations.

公开(公告)号：US20180173649A1

公开(公告)日：2018-06-21

申请号：US15385566

申请日：2016-12-20

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Rostyslav Kyrychynskyi ,  Anthony Asaro ,  Kostantinos Danny Christidis ,  Mark Fowler ,  Michael J. Mantor ,  Robert Scott Hartog

IPC: G06F13/16 ,  G06F13/40

CPC classification number: G06F13/161 ,  G06F13/1673 ,  G06F13/4068

Abstract: A system and method for efficient arbitration of memory access requests are described. One or more functional units generate memory access requests for a partitioned memory. An arbitration unit stores the generated requests and selects a given one of the stored requests. The arbitration unit identifies a given partition of the memory which stores a memory location targeted by the selected request. The arbitration unit determines whether one or more other stored requests access memory locations in the given partition. The arbitration unit sends each of the selected memory access request and the identified one or more other memory access requests to the memory to be serviced out of order.