公开(公告)号：US20230052676A1

公开(公告)日：2023-02-16

申请号：US17978533

申请日：2022-11-01

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Jean JIMENEZ MARTINEZ

IPC: H01L29/78 ,  H01L27/06 ,  H01L29/66 ,  H01L29/73 ,  H01L29/06

Abstract: An integrated circuit includes an N-type laterally diffused metal-oxide semiconductor (NLDMOS) transistor including an active semiconductor substrate region having P-type conductivity. The integrated circuit further includes a buried semiconductor region having N+-type conductivity underneath the active substrate region. The buried semiconductor region is more heavily doped than the active semiconductor substrate region.

公开(公告)号：US11555852B2

公开(公告)日：2023-01-17

申请号：US16249546

申请日：2019-01-16

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Patrick Le Maitre ,  Jean-Francois Carpentier

IPC: G01R31/317 ,  H01L25/16 ,  G02F1/21 ,  G02B6/28 ,  G02B6/12 ,  G02B6/27 ,  G02B6/293 ,  G01M11/00

Abstract: An optoelectronic chip includes optical inputs having different passbands, a photonic circuit to be tested, and an optical coupling device configured to couple said inputs to the photonic circuit to be tested.

公开(公告)号：US20230006132A1

公开(公告)日：2023-01-05

申请号：US17847016

申请日：2022-06-22

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Laurent FAVENNEC ,  Fausto PIAZZA

IPC: H01L45/00 ,  H01L27/24 ,  H01L23/522

Abstract: A method for making a phase change memory includes a step of forming an array of phase change memory cells, with each cell being separated from neighboring cells in the same line of the array and from neighboring cells in the same column of the array, by the same first distance. The method further includes a step of etching one memory cell out of N, with N being at least equal to 2, in each line or each column.

公开(公告)号：US20230005735A1

公开(公告)日：2023-01-05

申请号：US17940758

申请日：2022-09-08

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Delia RISTOIU ,  Pierre BAR ,  Francois LEVERD

IPC: H01L21/02 ,  H01L21/311

Abstract: The present disclosure relates to a method for forming a cavity that traverses a stack of layers including a bottom layer, a first portion of which locally presents an excess thickness, the method comprising a first step of non-selective etching and a second step of selective etching vertically in line with the first portion.

公开(公告)号：US11538719B2

公开(公告)日：2022-12-27

申请号：US17160598

申请日：2021-01-28

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Jean Jimenez Martinez

IPC: H01L21/82 ,  H01L21/8228 ,  H01L27/082

Abstract: A microelectronic device includes a PNP transistor and NPN transistor arranged vertically in a P-type doped semiconductor substrate. The PNP and NPN transistors are manufactured by: forming an N+ doped isolating well for the PNP transistor in the semiconductor substrate; forming a P+ doped region in the N+ doped isolating well; epitaxially growing a first semiconductor layer on the semiconductor substrate; forming an N+ doped well for the NPN transistor, where at least part of the N+ doped well extends into the first semiconductor layer; then epitaxially growing a second semiconductor layer on the first semiconductor layer; forming a P doped region forming the collector of the PNP transistor in the second semiconductor layer and in electrical contact with the P+ doped region; and forming an N doped region forming the collector of the NPN transistor in the second semiconductor layer and in electrical contact with the N+ doped well.

公开(公告)号：US11531224B2

公开(公告)日：2022-12-20

申请号：US16931202

申请日：2020-07-16

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sebastien Cremer

IPC: G02F1/1333 ,  G02B6/13 ,  G02F1/01

Abstract: A method includes forming a layer made of a first insulating material on a first layer made of a second insulating material that covers a support, defining a waveguide made of the first material in the layer of the first material, covering the waveguide made of the first material with a second layer of the second material, planarizing an upper surface of the second layer of the second material, and forming a single-crystal silicon layer over the second layer.

公开(公告)号：US20220320722A1

公开(公告)日：2022-10-06

申请号：US17701340

申请日：2022-03-22

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sebastien CREMER

IPC: H01Q1/38 ,  H01Q1/22 ,  H01Q1/00

Abstract: The present disclosure relates to a method of making an electronic device comprising a first wafer including at least one trench and a second wafer, the second wafer being bonded, by hybrid bonding, to the first wafer, so as to form, at the level of the trench, at least one enclosed space, empty or gas-filled.

公开(公告)号：US20220254905A1

公开(公告)日：2022-08-11

申请号：US17730691

申请日：2022-04-27

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Jean JIMENEZ MARTINEZ

IPC: H01L29/66 ,  H01L21/8248 ,  H01L27/06 ,  H01L29/06 ,  H01L29/808 ,  H01L29/423 ,  H01L27/112

Abstract: An integrated circuit includes a junction field-effect transistor formed in a semiconductor substrate. The junction field-effect transistor includes a drain region, a source region, a channel region, and a gate region. A first isolating region separates the drain region from both the gate region and the channel region. A first connection region connects the drain region to the channel region by passing underneath the first isolating region in the semiconductor substrate. A second isolating region separates the source region from both the gate region and the channel region. A second connection region connects the source region to the channel region by passing underneath the second isolating region in the semiconductor substrate.

公开(公告)号：US20220254879A1

公开(公告)日：2022-08-11

申请号：US17734486

申请日：2022-05-02

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Alexis GAUTHIER ,  Pascal CHEVALIER ,  Gregory AVENIER

IPC: H01L29/06 ,  H01L21/8222 ,  H01L29/66 ,  H01L29/732

Abstract: A transistor is produced by forming a first part of a first region of the transistor in a semiconductor substrate by implanting dopants through an opening in an isolating trench formed at an upper surface of the semiconductor substrate. A second region of the transistor in the opening by epitaxy.

公开(公告)号：US11411177B2

公开(公告)日：2022-08-09

申请号：US16879577

申请日：2020-05-20

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Philippe Boivin ,  Daniel Benoit ,  Remy Berthelon

IPC: H01L29/02 ,  H01L45/00 ,  H01L27/24

Abstract: The present disclosure concerns a phase-change memory manufacturing method and a phase-change memory device. The method includes forming a first insulating layer in cavities located vertically in line with strips of phase-change material, and anisotropically etching the portions of the first insulating layer located at the bottom of the cavities; and a phase-change memory device including a first insulating layer against lateral walls of cavities located vertically in line with strips of phase-change material.