公开(公告)号：US11010263B2

公开(公告)日：2021-05-18

申请号：US16254920

申请日：2019-01-23

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  J. James Tringali ,  Ely Tsern

IPC: G06F11/14 ,  G11C7/20 ,  G11C14/00 ,  G06F3/06

Abstract: The embodiments described herein describe technologies for non-volatile memory persistence in a multi-tiered memory system including two or more memory technologies for volatile memory and non-volatile memory.

公开(公告)号：US20210141748A1

公开(公告)日：2021-05-13

申请号：US17081909

申请日：2020-10-27

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Amir Amirkhany ,  Suresh Rajan ,  Mohammad Hekmat ,  Dinesh Patil

IPC: G06F13/16 ,  G11C7/10 ,  G11C8/18 ,  G11C11/419 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C5/02 ,  G06F13/40

Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.

公开(公告)号：US20210098280A1

公开(公告)日：2021-04-01

申请号：US17068717

申请日：2020-10-12

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  Ian P. Shaeffer

IPC: H01L21/768 ,  H01L25/065

Abstract: This application is directed to a system including a plurality of devices that are stacked one on top of another. Each device includes a substrate having two opposing surfaces. A first row of contacts is coupled on a first surface and includes a first contact and a second contact that are adjacent to each other. A second row of contacts is coupled on a respective second surface and includes a third contact. Each contact in the second row of contacts is physically aligned with an opposite contact in the first row. The third contact is disposed opposite and physically aligned with the first contact in the first row, and electrically coupled to the second contact in the first row. Operational circuitry is electrically coupled to at least the first contact on the first row, and at least two of the plurality of devices have distinct operational circuitry.

公开(公告)号：US20210064552A1

公开(公告)日：2021-03-04

申请号：US17022746

申请日：2020-09-16

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Frederick A. Ware

IPC: G06F12/14 ,  G06F3/06 ,  G06F13/16 ,  G06F12/02

Abstract: A multi-rank memory system in which calibration operations are performed between a memory controller and one rank of memory while data is transferred between the controller and other ranks of memory. A memory controller performs a calibration operation that calibrates parameters pertaining to transmission of data via a first data bus between the memory controller and a memory device in a first rank of memory. While the controller performs the calibration operation, the controller also transfers data with a memory device in a second rank of memory via a second data bus.

公开(公告)号：US20210042226A1

公开(公告)日：2021-02-11

申请号：US16618105

申请日：2018-05-15

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G06F12/0802

Abstract: A hybrid memory module includes cache of relatively fast and durable dynamic, random-access memory (DRAM) in service of a larger amount of relatively slow and wear-sensitive flash memory. An address buffer on the module maintains a static, random-access memory (SRAM) cache of addresses for data cached in DRAM. Together, the DRAM and SRAM caches hasten read and write access and reduce wear for a larger amount of nonvolatile memory.

公开(公告)号：US20200349991A1

公开(公告)日：2020-11-05

申请号：US16853612

申请日：2020-04-20

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  Brian S. Leibowitz ,  Wayne Frederick Ellis ,  Akash Bansal ,  John Welsford Brooks ,  Kishore Ven Kasamsetty

IPC: G11C8/18 ,  G11C29/02 ,  G06F13/16 ,  G11C7/10 ,  G11C5/02 ,  G06F13/42

Abstract: In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.

公开(公告)号：US20200348859A1

公开(公告)日：2020-11-05

申请号：US16875881

申请日：2020-05-15

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Robert E. Palmer ,  John W. Poulton

IPC: G06F3/06 ,  G06F13/16 ,  G06Q10/00 ,  G11C7/02 ,  G11C11/406 ,  G06Q20/00

Abstract: A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of a data interface circuit of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order.

公开(公告)号：US20200341932A1

公开(公告)日：2020-10-29

申请号：US16874439

申请日：2020-05-14

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G06F13/42

Abstract: An integrated circuit device is disclosed including core circuitry and interface circuitry. The core circuitry outputs in parallel a set of data bits, while the interface circuitry couples to the core circuitry. The interface circuitry receives in parallel a first number of data bits among the set of data bits from the core circuitry and outputs in parallel a second number of data bits. The ratio of the first number to the second number is a non-power-of-2 value.

公开(公告)号：US10804139B2

公开(公告)日：2020-10-13

申请号：US15824762

申请日：2017-11-28

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  Ian P. Shaeffer

IPC: H01L21/768 ,  H01L25/065

Abstract: This application is directed to a system including a plurality of devices that are stacked one on top of another. Each device includes a substrate having two opposing surfaces. A first row of contacts is coupled on a first surface and includes a first contact and a second contact that are adjacent to each other. A second row of contacts is coupled on a respective second surface and includes a third contact. Each contact in the second row of contacts is physically aligned with an opposite contact in the first row. The third contact is disposed opposite and physically aligned with the first contact in the first row, and electrically coupled to the second contact in the first row. Operational circuitry is electrically coupled to at least the first contact on the first row, and at least two of the plurality of devices have distinct operational circuitry.

公开(公告)号：US20200321048A1

公开(公告)日：2020-10-08

申请号：US16856596

申请日：2020-04-23

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth L. Wright

IPC: G11C11/4093 ,  G11C11/4096 ,  G06F11/10 ,  G11C7/02 ,  G11C29/52

Abstract: Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.