公开(公告)号：US20070009840A1

公开(公告)日：2007-01-11

申请号：US11480545

申请日：2006-07-05

Applicant: Dong-chan Kim ,  Chang-jin Kang ,  Kyeong-koo Chi

Inventor： Dong-chan Kim ,  Chang-jin Kang ,  Kyeong-koo Chi

IPC: G03F7/26

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/76816 ,  H01L21/76897 ,  Y10S438/947

Abstract: A method of fabricating a semiconductor device comprising a method of forming an etching mask used for etching a semiconductor base material is disclosed. The method of fabricating a semiconductor device comprises forming hard mask patterns on a semiconductor base material; forming material layers covering the lateral and top surfaces of the hard mask patterns to form openings between adjacent hard mask patterns, wherein the width of each opening is smaller than the distance between adjacent hard mask patterns; and etching the semiconductor base material using the hard mask patterns and material layers as an etching mask.

Abstract translation: 公开了一种制造半导体器件的方法，包括形成用于蚀刻半导体基底材料的蚀刻掩模的方法。 制造半导体器件的方法包括在半导体基底材料上形成硬掩模图案; 形成覆盖硬掩模图案的侧表面和顶表面的材料层，以在相邻的硬掩模图案之间形成开口，其中每个开口的宽度小于相邻硬掩模图案之间的距离; 并使用硬掩模图案和材料层作为蚀刻掩模蚀刻半导体基底材料。

公开(公告)号：US20050275042A1

公开(公告)日：2005-12-15

申请号：US11138034

申请日：2005-05-26

Applicant: Sung-Wook Hwang ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Sung-Hoon Chung

Inventor： Sung-Wook Hwang ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Sung-Hoon Chung

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/49 ,  H01L29/51 ,  H01L29/74

CPC classification number: H01L29/4236 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66553 ,  H01L29/66621

Abstract: A semiconductor device including a transistor and a method of forming thereof are provided. The semiconductor device comprises a metal gate electrode. A lower portion of the metal gate electrode fills a channel trench formed at a predetermined region of a substrate, and an upper portion of the metal gate electrode protrudes on the substrate. A gate insulating layer is interposed between inner sidewalls and a bottom surface of the channel trench, and the metal gate electrode. Source/drain regions are formed at the substrate in both sides of the metal gate electrode.

Abstract translation: 提供了包括晶体管及其形成方法的半导体器件。 半导体器件包括金属栅电极。 金属栅电极的下部填充形成在衬底的预定区域处的沟道沟槽，并且金属栅电极的上部在衬底上突出。 栅极绝缘层插入在沟道沟槽的内侧壁和底表面之间以及金属栅电极之间。 源极/漏极区域形成在金属栅电极两侧的衬底处。

公开(公告)号：US20050130354A1

公开(公告)日：2005-06-16

申请号：US10988584

申请日：2004-11-16

Applicant: Jin-young Kim ,  Maeda Shigenobu ,  Chang-jin Kang ,  Jeong-hwan Yang

Inventor： Jin-young Kim ,  Maeda Shigenobu ,  Chang-jin Kang ,  Jeong-hwan Yang

IPC: H01L21/335 ,  H01L21/00 ,  H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795

Abstract: A method of fabricating a MOS transistor, and the MOS transistor fabricated by the method, includes providing a substrate, forming a predetermined layer having a non-planar surface on the substrate, the predetermined layer including at least one active region, forming a gate electrode material layer on the non-planar, predetermined layer, forming a material layer and a hard mask layer on an entire surface of the gate electrode material layer, and planarizing a top surface of the material layer to form a planarized material layer, forming a photoresist pattern on the planarized material layer and the hard mask layer to pattern the gate electrode material layer, forming a hard mask pattern by etching the hard mask layer using the photoresist pattern as an etching mask, and forming a predetermined pattern by etching the planarized material layer and the gate electrode material layer according to a shape of the hard mask pattern.

Abstract translation: 制造MOS晶体管的方法和通过该方法制造的MOS晶体管包括提供衬底，在衬底上形成具有非平面表面的预定层，所述预定层包括至少一个有源区，形成栅电极 在非平面预定层上形成材料层，在栅电极材料层的整个表面上形成材料层和硬掩模层，并且平坦化材料层的顶表面以形成平坦化的材料层，形成光致抗蚀剂 在平坦化材料层和硬掩模层上形成图案以图案化栅电极材料层，通过使用光致抗蚀剂图案蚀刻硬掩模层作为蚀刻掩模形成硬掩模图案，并通过蚀刻平坦化材料层形成预定图案 以及根据硬掩模图案的形状的栅电极材料层。

公开(公告)号：US20050003310A1

公开(公告)日：2005-01-06

申请号：US10802150

申请日：2004-03-17

Applicant: Keun-Hee Bai ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Myeong-Cheol Kim

Inventor： Keun-Hee Bai ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Myeong-Cheol Kim

IPC: H01L21/3065 ,  G03F7/36 ,  G03F7/40 ,  H01L21/027 ,  H01L21/311

CPC classification number: G03F7/40 ,  H01L21/0276 ,  H01L21/31144

Abstract: An etching process including plasma pretreatment for generating a polymer layer formed of carbon on a photoresist pattern. The photoresist pattern is treated with plasma that does not contain fluorine radicals and that provides carbon radicals. An etching process is performed on an etching target layer by using the photoresist pattern as an etch mask.

Abstract translation: 一种蚀刻工艺，包括用于在光致抗蚀剂图案上产生由碳形成的聚合物层的等离子体预处理。 用不含氟自由基并提供碳自由基的等离子体处理光致抗蚀剂图案。 通过使用光致抗蚀剂图案作为蚀刻掩模，在蚀刻目标层上进行蚀刻处理。

公开(公告)号：US06753221B2

公开(公告)日：2004-06-22

申请号：US10322274

申请日：2002-12-17

Applicant: Jeong-Sic Jeon ,  Chang-Jin Kang ,  Seung-Young Son ,  Jin-Hong Kim

Inventor： Jeong-Sic Jeon ,  Chang-Jin Kang ,  Seung-Young Son ,  Jin-Hong Kim

IPC: H01L218242

CPC classification number: H01L27/10852 ,  H01L21/31116 ,  H01L21/32136 ,  H01L27/10894 ,  H01L28/55 ,  H01L28/91

Abstract: Methods for fabricating semiconductor devices having capacitors are provided. A plurality of storage node electrodes are formed on a semiconductor substrate. Then, a capacitor dielectric layer is formed over the storage node electrodes. A plate electrode layer is subsequently formed on the capacitor dielectric layer. A hard mask layer is then formed on the resultant structure where the plate electrode layer is formed so as to fill a gap between the adjacent storage node electrodes. The hard mask layer and the plate electrode layer are successively patterned to form a plate electrode.

Abstract translation: 提供了制造具有电容器的半导体器件的方法。 多个存储节点电极形成在半导体衬底上。 然后，在存储节点电极上形成电容器电介质层。 随后在电容器电介质层上形成平板电极层。 然后在其上形成平板电极层的所得结构上形成硬掩模层，以填充相邻存储节点电极之间的间隙。 硬掩模层和平板电极层依次构图以形成平板电极。

公开(公告)号：US06607954B2

公开(公告)日：2003-08-19

申请号：US10304273

申请日：2002-11-26

Applicant: Jeong-sic Jeon ,  Kyeong-koo Chi ,  Chang-jin Kang ,  Jin-hwan Hahm

Inventor： Jeong-sic Jeon ,  Kyeong-koo Chi ,  Chang-jin Kang ,  Jin-hwan Hahm

IPC: H01L218242

CPC classification number: H01L27/10852 ,  H01L21/76895 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/91

Abstract: A capacitor for a semiconductor memory device is fabricated by forming a mold layer on a semiconductor substrate that includes a peripheral circuit area and a cell array area which includes a plug in a buried contact hole. A hard mask layer pattern is formed on the mold layer. The mold layer is etched, using the hard mask layer pattern as an etch mask, to form a mold layer pattern. The hard mask layer pattern is then removed from the mold layer pattern or only partially etched back on the mold layer pattern. A capacitor lower electrode is formed along the walls of the buried contact hole and on a surface of the mold layer pattern. A capacitor dielectric layer is formed on the capacitor lower electrode and a capacitor upper electrode is formed on the capacitor dielectric layer.

Abstract translation: 半导体存储器件的电容器是通过在包括外围电路区域的半导体衬底上形成模层而形成的，以及包括埋入接触孔中的插头的单元阵列区域。 在模具层上形成硬掩模层图案。 使用硬掩模层图案作为蚀刻掩模蚀刻模具层以形成模具层图案。 然后将硬掩模层图案从模具层图案中移除，或者仅在模具层图案上部分地蚀刻回去。 电容器下电极沿掩埋接触孔的壁和模层图案的表面形成。 在电容器下电极上形成电容器电介质层，在电容器电介质层上形成电容器上电极。