公开(公告)号：US20210335431A1

公开(公告)日：2021-10-28

申请号：US15405346

申请日：2017-01-13

申请人： CHANG-MIN CHOI ,  BONG-YONG LEE ,  DONG-CHAN KIM ,  SU-JIN AHN

发明人： CHANG-MIN CHOI ,  BONG-YONG LEE ,  DONG-CHAN KIM ,  SU-JIN AHN

IPC分类号： G11C16/34 ,  G11C16/10 ,  G11C16/28 ,  G11C16/30 ,  G11C16/08 ,  G11C16/32

摘要： A method of programming a non-volatile memory includes executing at least two program loops on memory cells in a selected word line, generating a fail bit trend based on a result of executing each of the at least two program loops, predicting a plurality of program loops comprising an N program loop to be executed last on the memory cells, based on the generated fail bit trend, and changing, based on a result of predicting the plurality of program loops, a level of an N program voltage provided to the memory cells when the N program loop is executed.

公开(公告)号：US20170062059A1

公开(公告)日：2017-03-02

申请号：US15245162

申请日：2016-08-23

申请人： Yoon KIM ,  Dong-chan KIM ,  Ji-sang LEE

发明人： Yoon KIM ,  Dong-chan KIM ,  Ji-sang LEE

IPC分类号： G11C16/14 ,  G11C16/34 ,  G11C16/08 ,  G11C16/04

CPC分类号： G11C16/14 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/107 ,  G11C16/349

摘要： A memory device, comprising: a memory cell array including a plurality of NAND strings, each NAND string including a plurality of memory cells respectively connected to a plurality of word lines vertically stacked on a substrate; and a control logic configured to generate a pre-programming control signal for memory cells of a first NAND string of the NAND strings such that, before erasing the memory cells of the first NAND string, pre-programming voltages applied to the word lines coupled to the corresponding memory cells of the first NAND string vary based on an operating characteristic of the corresponding memory cells.

摘要翻译： 一种存储器件，包括：包括多个NAND串的存储单元阵列，每个NAND串包括分别连接到垂直堆叠在衬底上的多个字线的多个存储器单元; 以及控制逻辑，被配置为为NAND串的第一NAND串的存储器单元生成预编程控制信号，使得在擦除第一NAND串的存储单元之前，将预编程电压施加到耦合到 第一NAND串的对应存储单元基于相应的存储单元的工作特性而变化。

公开(公告)号：US09484219B2

公开(公告)日：2016-11-01

申请号：US14826845

申请日：2015-08-14

申请人： Young-Geun Park ,  Wook-Yeol Yi ,  Sang-Yeol Kang ,  Dong-Chan Kim ,  Chang-Mu An ,  Bong-Hyun Kim ,  Han-Jin Lim

发明人： Young-Geun Park ,  Wook-Yeol Yi ,  Sang-Yeol Kang ,  Dong-Chan Kim ,  Chang-Mu An ,  Bong-Hyun Kim ,  Han-Jin Lim

IPC分类号： H01L21/8242 ,  H01L21/311 ,  H01L27/108

CPC分类号： H01L21/31144 ,  H01L21/31111 ,  H01L21/31116 ,  H01L27/10852 ,  H01L27/10855

摘要： A method of fabricating semiconductor devices may include forming a mold structure on a lower layer, the mold structure including an etch stop layer doped at a first impurity concentration, a lower mold layer doped at a second impurity concentration, and an undoped upper mold layer. The method may include forming a trench exposing the lower layer in the mold structure using dry etching, extending a width of the trench in the etch stop layer using wet etching, and forming a first conductive pattern in the extended width trench, wherein an etch rate of the etch stop layer with respect to the dry etching may be smaller than an etch rate of the lower mold layer with respect to the dry etching, and an etch rate of the etch stop layer with respect to the wet etching may be proportional to the first impurity concentration.

摘要翻译： 制造半导体器件的方法可以包括在下层上形成模具结构，所述模具结构包括以第一杂质浓度掺杂的蚀刻停止层，以第二杂质浓度掺杂的下模层和未掺杂的上模层。 该方法可以包括使用干蚀刻形成在模具结构中暴露下层的沟槽，使用湿蚀刻在蚀刻停止层中延伸沟槽的宽度，以及在扩展宽度沟槽中形成第一导电图案，其中蚀刻速率 相对于干蚀刻的蚀刻停止层的蚀刻速度可以小于相对于干蚀刻的下模层的蚀刻速率，并且蚀刻停止层相对于湿蚀刻的蚀刻速率可以与 第一杂质浓度。

公开(公告)号：US20160064386A1

公开(公告)日：2016-03-03

申请号：US14826845

申请日：2015-08-14

申请人： Young-Geun PARK ,  Wook-Yeol YI ,  Sang-Yeol KANG ,  Dong-Chan KIM ,  Chang-Mu AN ,  Bong-Hyun KIM ,  Han-Jin LIM

发明人： Young-Geun PARK ,  Wook-Yeol YI ,  Sang-Yeol KANG ,  Dong-Chan KIM ,  Chang-Mu AN ,  Bong-Hyun KIM ,  Han-Jin LIM

IPC分类号： H01L27/108 ,  H01L21/311

CPC分类号： H01L21/31144 ,  H01L21/31111 ,  H01L21/31116 ,  H01L27/10852 ,  H01L27/10855

摘要： A method of fabricating semiconductor devices may include forming a mold structure on a lower layer, the mold structure including an etch stop layer doped at a first impurity concentration, a lower mold layer doped at a second impurity concentration, and an undoped upper mold layer. The method may include forming a trench exposing the lower layer in the mold structure using dry etching, extending a width of the trench in the etch stop layer using wet etching, and forming a first conductive pattern in the extended width trench, wherein an etch rate of the etch stop layer with respect to the dry etching may be smaller than an etch rate of the lower mold layer with respect to the dry etching, and an etch rate of the etch stop layer with respect to the wet etching may be proportional to the first impurity concentration.

摘要翻译： 制造半导体器件的方法可以包括在下层上形成模具结构，所述模具结构包括以第一杂质浓度掺杂的蚀刻停止层，以第二杂质浓度掺杂的下模层和未掺杂的上模层。 该方法可以包括使用干蚀刻形成在模具结构中暴露下层的沟槽，使用湿蚀刻在蚀刻停止层中延伸沟槽的宽度，以及在扩展宽度沟槽中形成第一导电图案，其中蚀刻速率 相对于干蚀刻的蚀刻停止层的蚀刻速度可以小于相对于干蚀刻的下模层的蚀刻速率，并且蚀刻停止层相对于湿蚀刻的蚀刻速率可以与 第一杂质浓度。

公开(公告)号：US09190495B2

公开(公告)日：2015-11-17

申请号：US12563473

申请日：2009-09-21

申请人： Jeong-Do Ryu ,  Dong-Chan Kim ,  Seong-Hoon Jeong ,  Si-Young Choi ,  Yu-Gyun Shin ,  Tai-Su Park ,  Jong-Ryeol Yoo ,  Jong-Hoon Kang

发明人： Jeong-Do Ryu ,  Dong-Chan Kim ,  Seong-Hoon Jeong ,  Si-Young Choi ,  Yu-Gyun Shin ,  Tai-Su Park ,  Jong-Ryeol Yoo ,  Jong-Hoon Kang

IPC分类号： H01L27/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L29/423 ,  H01L29/51 ,  H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/66795 ,  H01L21/28211 ,  H01L21/823412 ,  H01L27/105 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/10894 ,  H01L27/11 ,  H01L29/4236 ,  H01L29/51 ,  H01L29/66621 ,  H01L29/7851

摘要： A recessed channel array transistor may include a substrate, a gate oxide layer, a gate electrode and source/drain regions. The substrate may have an active region and an isolation region. A recess may be formed in the active region. The gate oxide layer may be formed on the recess and the substrate. The gate oxide layer may include a first portion on an intersection between a side end of the recess and a sidewall of the active region and a second portion on a side surface of the recess. The first portion may include a thickness greater than about 70% of a thickness of the second portion. The gate electrode may be formed on the gate oxide layer. The source/drain regions may be formed in the substrate. Thus, the recessed channel array transistor may have a decreased leakage current and an increased on-current.

摘要翻译： 凹陷通道阵列晶体管可以包括衬底，栅极氧化物层，栅极电极和源极/漏极区域。 衬底可以具有有源区和隔离区。 可以在活性区域中形成凹部。 栅极氧化物层可以形成在凹部和基板上。 栅极氧化物层可以包括在凹部的侧端和有源区的侧壁与凹部的侧表面上的第二部分之间的交叉处的第一部分。 第一部分可以包括大于第二部分厚度的约70％的厚度。 栅极电极可以形成在栅极氧化物层上。 源极/漏极区域可以形成在衬底中。 因此，凹陷通道阵列晶体管可能具有减小的漏电流和增加的导通电流。

公开(公告)号：US08310055B2

公开(公告)日：2012-11-13

申请号：US12645820

申请日：2009-12-23

申请人： Young-ju Park ,  Jae-ho Min ,  Myeong-cheol Kim ,  Dong-chan Kim ,  Jae-hwang Sim

发明人： Young-ju Park ,  Jae-ho Min ,  Myeong-cheol Kim ,  Dong-chan Kim ,  Jae-hwang Sim

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L23/528 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L23/522 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11531 ,  H01L27/11548 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices and methods of forming semiconductor devices are provided in which a plurality of patterns are simultaneously formed to have different widths and the pattern densities of some regions are increased using double patterning. The semiconductor device includes a plurality of conductive lines each including a first line portion and a second line portion, where the first line portion extends on a substrate in a first direction, the second line portion extends from one end of the first line portion in a second direction, and the first direction is different from the second direction; a plurality of contact pads each of which is connected with a respective conductive line of the plurality of conductive lines via the second line portion of the corresponding conductive line; and a plurality of dummy conductive lines each including a first dummy portion extending from a respective contact pad of the plurality of contact pads, in parallel with the corresponding second line portion in the second direction.

摘要翻译： 提供形成半导体器件的半导体器件和方法，其中同时形成多个图案以具有不同的宽度，并且使用双重图案化来增加一些区域的图案密度。 半导体器件包括多个导线，每条导线包括第一线部分和第二线部分，其中第一线部分在第一方向上在衬底上延伸，第二线部分从第一线部分的一端延伸到 第二方向，第一方向与第二方向不同; 多个接触焊盘，每个接触焊盘经由相应的导线的第二线部分与多条导线的相应导线连接; 以及多个虚设导电线，每个虚设导电线包括从所述多个接触焊盘的相应的接触焊盘延伸的第一虚设部分，与所述第二方向上的对应的第二线部分平行。

公开(公告)号：US08252681B2

公开(公告)日：2012-08-28

申请号：US12536865

申请日：2009-08-06

申请人： Jeong-Do Ryu ,  Si-Young Choi ,  Yu-Gyun Shin ,  Tai-Su Park ,  Dong-Chan Kim ,  Jong-Ryeol Yoo ,  Seong-Hoon Jeong ,  Jong-Hoon Kang

发明人： Jeong-Do Ryu ,  Si-Young Choi ,  Yu-Gyun Shin ,  Tai-Su Park ,  Dong-Chan Kim ,  Jong-Ryeol Yoo ,  Seong-Hoon Jeong ,  Jong-Hoon Kang

IPC分类号： H01L21/44

CPC分类号： H01L21/28061 ,  H01L21/28247 ,  H01L21/3211 ,  H01L21/32137 ,  H01L21/32139 ,  H01L27/10873 ,  H01L27/11 ,  H01L27/1104

摘要： Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer.

摘要翻译： 形成集成电路器件的方法包括在衬底上形成含硅的导电层，并在导电层上形成掩模图案。 使用掩模图案作为蚀刻掩模，选择性地蚀刻导电层以限定其上的第一侧壁。 可以将导电层的第一侧壁暴露于氮等离子体，从而在第一侧壁上形成第一氮化硅层。 然后再次选择性地蚀刻导电层以暴露其上没有第一氮化硅层的第二侧壁。 在选择性蚀刻导电层的第二步骤期间，掩模图案可以再次用作蚀刻掩模。

公开(公告)号：US07338849B2

公开(公告)日：2008-03-04

申请号：US11261820

申请日：2005-10-28

申请人： Dong-Chan Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Dong-Hyun Kim

发明人： Dong-Chan Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Dong-Hyun Kim

IPC分类号： H01L21/8238 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： Methods of fabricating a flash memory device and flash memory devices fabricated thereby are provided. One of the methods includes forming an isolation layer in a semiconductor substrate to define a plurality of parallel active regions in the semiconductor substrate. A plurality of first conductive layer patterns are formed on the active regions. The first conductive layer patterns are spaced apart from each other in a lengthwise direction of the active regions. An insulating layer is conformally formed on the semiconductor substrate and the first conductive layer patterns. A second conductive layer is formed on the insulating layer. The second conductive layer is patterned until the insulating layer is exposed to form a plurality of parallel second conductive layer patterns. The second conductive layer patterns cross the active regions and the isolation layer to overlap the first conductive layer patterns.

摘要翻译： 提供了制造闪速存储器件的方法和由此制造的闪存器件。 一种方法包括在半导体衬底中形成隔离层以在半导体衬底中限定多个平行的有源区。 在有源区上形成多个第一导电层图案。 第一导电层图案在活性区域的长度方向上彼此间隔开。 在半导体衬底和第一导电层图案上共形形成绝缘层。 在绝缘层上形成第二导电层。 图案化第二导电层直到绝缘层暴露以形成多个平行的第二导电层图案。 第二导电层图案与有源区和隔离层交叉，以与第一导电层图案重叠。

公开(公告)号：US20080032512A1

公开(公告)日：2008-02-07

申请号：US11828541

申请日：2007-07-26

申请人： Dong-Chan KIM ,  Seong-Hoon JEONG ,  Myoung-Bum LEE ,  Sang-Bom KANG ,  Jin-Hwa HEO

发明人： Dong-Chan KIM ,  Seong-Hoon JEONG ,  Myoung-Bum LEE ,  Sang-Bom KANG ,  Jin-Hwa HEO

IPC分类号： H01L21/31

CPC分类号： H01L21/0214 ,  H01L21/02252 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/28202 ,  H01L21/3144 ,  H01L29/518 ,  H01L29/78

摘要： A method of manufacturing a semiconductor device in a process camber is disclosed. The method includes forming a preliminary dielectric layer including oxynitride on a substrate by performing a plasma oxidation treatment and a first plasma nitridation treatment, wherein the preliminary dielectric layer has a substantially uniform nitrogen concentration profile to a defined depth, and forming a dielectric layer from the preliminary dielectric layer by performing a second plasma nitridation treatment, wherein the nitrogen concentration of the dielectric layer is higher than that of the preliminary dielectric layer.

摘要翻译： 公开了一种制造半导体器件的方法。 该方法包括通过进行等离子体氧化处理和第一等离子体氮化处理在衬底上形成包括氧氮化物的预备电介质层，其中预备电介质层具有基本上均匀的氮浓度分布到规定的深度，并且从 通过进行第二等离子体氮化处理，其中所述电介质层的氮浓度高于所述预备介电层的氮浓度。

公开(公告)号：US20080020741A1

公开(公告)日：2008-01-24

申请号：US11806576

申请日：2007-06-01

申请人： Dong Chan Kim

发明人： Dong Chan Kim

IPC分类号： H04B1/38 ,  H04M3/42

CPC分类号： H04M1/2745 ,  H04M1/7258 ,  H04M2250/60

摘要： A speed dial setting method in a mobile communication terminal user interface and a mobile communication terminal are provided. In a conventional speed dial setting method, a speed dial is set only through entering a speed dial setting menu, which is a sub menu of an address book, whereby there is a limitation in conveniently setting a speed dial by a user. The speed dial setting method in a mobile communication terminal user interface and a mobile communication terminal can set a speed dial by inputting a key for an extended period using a contact list or a recent communication list. Therefore, because a speed dial can be set in a contact list or a recent communication list that can include phone numbers stored in a mobile communication terminal, a user can conveniently set a speed dial without entering a speed dial setting menu.

摘要翻译： 提供了一种在移动通信终端用户界面和移动通信终端中的快速拨号设定方法。 在常规的快速拨号设置方法中，仅通过进入作为地址簿的子菜单的快速拨号设置菜单来设置快速拨号，由此在用户方便地设置快速拨号时存在限制。 移动通信终端用户接口和移动通信终端中的快速拨号设定方法可以通过使用联系人列表或最近的通信列表输入长时间的密钥来设置快速拨号。 因此，由于可以在可以包括存储在移动通信终端中的电话号码的联系人列表或最近的通信列表中设置快速拨号，所以用户可以方便地设置快速拨号而不进入快速拨号设置菜单。