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272 条记录 (耗时 0.023 秒)

    Circuit device including vertical transistors connected to buried bitlines and method of manufacturing the same
    71.
    发明授权
    Circuit device including vertical transistors connected to buried bitlines and method of manufacturing the same 有权
    电路装置包括连接到埋地位线的垂直晶体管及其制造方法

    公开(公告)号：US07586149B2

    公开(公告)日：2009-09-08

    申请号：US11541756

    申请日：2006-10-02

    申请人： Jae-man Yoon ,  Dong-gun Park ,  Kang-yoon Lee ,  Choong-ho Lee ,  Bong-soo Kim ,  Seong-goo Kim ,  Hyeoung-won Seo ,  Seung-bae Park

    发明人： Jae-man Yoon ,  Dong-gun Park ,  Kang-yoon Lee ,  Choong-ho Lee ,  Bong-soo Kim ,  Seong-goo Kim ,  Hyeoung-won Seo ,  Seung-bae Park

    IPC分类号： H01L23/528 ,  H01L27/108

    CPC分类号： H01L29/66666 ,  H01L21/823885 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10894 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A circuit device including vertical transistors connected to buried bitlines and a method of manufacturing the circuit device. The circuit device includes a semiconductor substrate including a peripheral circuit region and left and right cell regions at both sides of the peripheral circuit region, bottom active regions arranged on the semiconductor substrate to be spaced apart from one another in a column direction and to extend from the peripheral circuit region alternately to the left cell region and the right cell region in a row direction, channel pillars protruding from the bottom active regions in a vertical direction and arranged to be aligned in the row direction and spaced apart from one another, gate electrodes provided with a gate dielectric layer and attached to surround side surfaces of the channel pillars, and buried bitlines extending along the bottom active regions, the bottom active regions including a bottom source/drain region.

    摘要翻译： 一种包括连接到掩埋位线的垂直晶体管的电路器件和制造该电路器件的方法。 该电路装置包括半导体衬底，该半导体衬底包括外围电路区域和在外围电路区域的两侧的左侧和右侧电池区域，布置在半导体衬底上的底部有源区域在列方向上彼此间隔开并从 所述外围电路区域与所述左侧单元区域和右侧单元区域交替地排列成行方向，所述通道柱从所述底部有源区域沿垂直方向突出并且被配置为在所述行方向上彼此对准并且彼此间隔开，栅电极 设置有栅介电层并且被附接到环绕通道柱的侧表面，以及沿底部有源区延伸的掩埋位线，底部有源区包括底部源极/漏极区。

    Semiconductor device employing buried insulating layer and method of fabricating the same
    72.
    发明授权
    Semiconductor device employing buried insulating layer and method of fabricating the same 失效
    采用埋层绝缘层的半导体器件及其制造方法

    公开(公告)号：US07575964B2

    公开(公告)日：2009-08-18

    申请号：US11944260

    申请日：2007-11-21

    申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Jeong-Dong Choe ,  Kyoung-Hwan Yeo

    发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Jeong-Dong Choe ,  Kyoung-Hwan Yeo

    IPC分类号： H01L21/337

    CPC分类号： H01L29/66651 ,  H01L27/10873 ,  H01L29/0653 ,  H01L29/66659

    摘要： A semiconductor device employs an asymmetrical buried insulating layer, and a method of fabricating the same. The semiconductor device includes a lower semiconductor substrate. An upper silicon pattern is located on the lower semiconductor substrate. The upper silicon pattern includes a channel region, and a source region and a drain region spaced apart from each other by the channel region. A gate electrode is electrically insulated from the upper silicon pattern and intersects over the channel region. A bit line and a cell capacitor are electrically connected to the source region and the drain region, respectively. A buried insulating layer is interposed between the drain region and the lower semiconductor substrate. The buried insulating layer has an extension portion partially interposed between the channel region and the lower semiconductor substrate.

    摘要翻译： 半导体器件采用非对称埋层绝缘层及其制造方法。 半导体器件包括下半导体衬底。 上硅图案位于下半导体衬底上。 上部硅图案包括通道区域以及由沟道区域彼此间隔开的源极区域和漏极区域。 栅电极与上硅图案电绝缘，并且在沟道区域上相交。 位线和单元电容器分别电连接到源极区域和漏极区域。 掩埋绝缘层插入在漏区和下半导体衬底之间。 掩埋绝缘层具有部分插入在沟道区域和下半导体衬底之间的延伸部分。

    Semiconductor Memory Devices Including a Vertical Channel Transistor
    73.
    发明申请
    Semiconductor Memory Devices Including a Vertical Channel Transistor 有权
    包括垂直通道晶体管的半导体存储器件

    公开(公告)号：US20090189217A1

    公开(公告)日：2009-07-30

    申请号：US12418879

    申请日：2009-04-06

    申请人： Jae-man Yoon ,  Dong-gun Park ,  Choong-ho Lee ,  Moon-suk Yi ,  Chul Lee

    发明人： Jae-man Yoon ,  Dong-gun Park ,  Choong-ho Lee ,  Moon-suk Yi ,  Chul Lee

    IPC分类号： H01L29/78

    CPC分类号： H01L27/10885 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10876 ,  H01L29/66666

    摘要： Semiconductor memory devices include a semiconductor substrate and a plurality of semiconductor material pillars in a spaced relationship on the semiconductor substrate. Respective surrounding gate electrodes surround ones of the pillars. A first source/drain region is in the semiconductor substrate between adjacent ones of the pillars and a second source/drain region is in an upper portion of at least one of the adjacent pillars. A buried bit line is in the first source/drain region and electrically coupled to the first source/drain region and a storage node electrode is on the upper portion of the at least one of the adjacent pillars and electrically contacting with the second source/drain region.

    摘要翻译： 半导体存储器件包括在半导体衬底上具有间隔关系的半导体衬底和多个半导体材料柱。 相邻的围绕电极围绕其中的一个柱。 第一源极/漏极区域在相邻的柱之间的半导体衬底中，并且第二源极/漏极区域位于至少一个相邻支柱的上部。 掩埋位线在第一源极/漏极区域中并且电耦合到第一源极/漏极区域，并且存储节点电极在相邻柱的至少一个的上部上并且与第二源极/漏极 地区。

    Method of forming fin field effect transistor using damascene process
    74.
    发明授权
    Method of forming fin field effect transistor using damascene process 有权
    使用镶嵌工艺形成翅片场效应晶体管的方法

    公开(公告)号：US07528022B2

    公开(公告)日：2009-05-05

    申请号：US11112818

    申请日：2005-04-21

    申请人： Young-Joon Ahn ,  Dong-Gun Park ,  Choong-Ho Lee ,  Hee-Soo Kang

    发明人： Young-Joon Ahn ,  Dong-Gun Park ,  Choong-Ho Lee ,  Hee-Soo Kang

    IPC分类号： H01L21/8234

    CPC分类号： H01L29/7851 ,  H01L21/26586 ,  H01L29/66818

    摘要： A method of forming a fin transistor using a damascene process is provided. A filling mold insulation pattern is recessed to expose an upper portion of a fin, and a mold layer is formed. The mold layer is patterned to form a groove crossing the fin and exposing a part of the upper portion of the fin. A gate electrode is formed to fill the groove with a gate insulation layer interposed between the fin and the gate electrode, and the mold layer is removed. Impurities are implanted through both sidewalls and a top surface of the upper portion of the fin disposed at opposite sides of a gate electrode to form a source/drain region.

    摘要翻译： 提供了一种使用镶嵌工艺形成鳍式晶体管的方法。 填充模具绝缘图案凹入以暴露翅片的上部，并且形成模具层。 图案化模具层以形成与散热片交叉的凹槽并暴露翅片上部的一部分。 形成栅电极，用插入翅片和栅电极之间的栅极绝缘层填充凹槽，并且去除模层。 通过设置在栅极电极的相对侧的翅片的上侧部分的两个侧壁和顶部表面注入杂质以形成源极/漏极区域。

    Non-volatile memory device and methods of forming the same
    76.
    发明授权
    Non-volatile memory device and methods of forming the same 有权
    非易失性存储器件及其形成方法

    公开(公告)号：US07465985B2

    公开(公告)日：2008-12-16

    申请号：US11580086

    申请日：2006-10-13

    申请人： Byung-Yong Choi ,  Choong-Ho Lee ,  Dong-Gun Park

    发明人： Byung-Yong Choi ,  Choong-Ho Lee ,  Dong-Gun Park

    IPC分类号： H01L21/334

    CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529

    摘要： A non-volatile memory device and a method of forming the same are provided. The non-volatile memory device may include a cell isolation pattern and a semiconductor pattern sequentially stacked on a predetermined or given region of a semiconductor substrate, a cell gate line on the semiconductor pattern and on a top surface of the semiconductor substrate on one side of the cell isolation pattern, a multi-layered trap insulation layer between the cell gate line and the semiconductor substrate, and the cell gate line and the semiconductor pattern, a first impurity diffusion layer in the semiconductor substrate on both sides of the cell gate line and a second impurity diffusion layer in the semiconductor pattern on both sides of the cell gate line.

    摘要翻译： 提供了一种非易失性存储器件及其形成方法。 非易失性存储器件可以包括依次层叠在半导体衬底的预定或给定区域上的单元隔离图案和半导体图案，半导体图案上的单元栅极线和半导体衬底的一侧的顶表面上的半导体图案 电池隔离图案，单元栅极线和半导体衬底之间的多层陷阱绝缘层，以及单元栅极线和半导体图案，在单元栅极线的两侧的半导体衬底中的第一杂质扩散层和 位于单元栅极线两侧的半导体图案中的第二杂质扩散层。

    TRANSISTOR HAVING GATE DIELECTRIC LAYER OF PARTIAL THICKNESS DIFFERENCE AND METHOD OF FABRICATING THE SAME
    77.
    发明申请
    TRANSISTOR HAVING GATE DIELECTRIC LAYER OF PARTIAL THICKNESS DIFFERENCE AND METHOD OF FABRICATING THE SAME 审中-公开
    具有部分厚度差异的栅介质层的晶体管及其制造方法

    公开(公告)号：US20080283879A1

    公开(公告)日：2008-11-20

    申请号：US12182593

    申请日：2008-07-30

    申请人： Byung-yong Choi ,  Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim

    发明人： Byung-yong Choi ,  Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim

    IPC分类号： H01L29/00

    CPC分类号： H01L21/26586 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/7833 ,  H01L29/7834

    摘要： A transistor having a gate dielectric layer of partial thickness difference and a method of fabricating the same are provided. The method includes forming a gate dielectric layer having a main portion with a relatively thin thickness formed on a semiconductor substrate, and a sidewall portion with a relatively thick thickness formed on both sides of the main portion. A first gate is formed overlapping the main portion of the gate dielectric layer, and forming a second gate layer covering the sidewall portion of the gate dielectric layer and covering the first gate. The second gate layer is etched, thereby forming second gates patterned with a spacer shape on sidewalls of the first gate. The exposed sidewall portion of the gate dielectric layer is selectively etched using the second gates as a mask, thereby forming a pattern of the gate dielectric layer to be aligned with the second gates. A source/drain is formed in a portion of the semiconductor substrate exposed by the second gates.

    摘要翻译： 提供具有部分厚度差的栅极介电层的晶体管及其制造方法。 该方法包括形成具有形成在半导体衬底上的较薄厚度的主要部分的栅介质层，以及形成在主体两侧的较厚厚度的侧壁部分。 第一栅极形成为与栅介质层的主要部分重叠，并形成覆盖栅介质层的侧壁部分并覆盖第一栅极的第二栅极层。 蚀刻第二栅极层，从而形成在第一栅极的侧壁上以间隔物形状图案化的第二栅极。 使用第二栅极作为掩模来选择性地蚀刻栅极电介质层的暴露的侧壁部分，从而形成与第二栅极对准的栅极电介质层的图案。 在由第二栅极暴露的半导体衬底的一部分中形成源极/漏极。

    Recessed transistor and method of manufacturing the same
    78.
    发明申请
    Recessed transistor and method of manufacturing the same 有权
    嵌入式晶体管及其制造方法

    公开(公告)号：US20080185641A1

    公开(公告)日：2008-08-07

    申请号：US12068179

    申请日：2008-02-04

    申请人： Keun-Nam Kim ,  Makoto Yoshida ,  Chul Lee ,  Dong-Gun Park ,  Woun-Suck Yang

    发明人： Keun-Nam Kim ,  Makoto Yoshida ,  Chul Lee ,  Dong-Gun Park ,  Woun-Suck Yang

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/66795 ,  H01L29/66621 ,  H01L29/7834 ,  H01L29/7851

    摘要： A recessed transistor and a method of manufacturing the same are provided. The recessed transistor may include a substrate, an active pin, a gate pattern and source and drain regions. The substrate may include an isolation layer that establishes an active region and a field region of the substrate. The substrate may include a recessed structure having an upper recess formed in the active region and a lower recess in communication with the upper recess. An active pin may be formed in a region between side surfaces of the isolation layer and the lower recess and an interface between the active region and the field region. The gate pattern may include a gate insulation layer formed on an inner surface of the recessed structure and a gate electrode formed on the gate insulation layer in the recessed structure. The source/drain regions may be formed adjacent to the active region and the gate electrode.

    摘要翻译： 提供凹陷晶体管及其制造方法。 凹陷的晶体管可以包括衬底，有源引脚，栅极图案以及源极和漏极区域。 衬底可以包括建立衬底的有源区和场区的隔离层。 衬底可以包括具有形成在有源区域中的上凹部的凹陷结构和与上凹部连通的下凹部。 有源销可以形成在隔离层和下凹部的侧表面之间的区域中以及有源区域和场区域之间的界面。 栅极图案可以包括形成在凹陷结构的内表面上的栅极绝缘层和形成在凹陷结构中的栅极绝缘层上的栅电极。 源/漏区可以与有源区和栅电极相邻形成。