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    Non-volatile memory devices and methods of forming the same
    2.
    发明申请
    Non-volatile memory devices and methods of forming the same 有权
    非易失性存储器件及其形成方法

    公开(公告)号：US20070090449A1

    公开(公告)日：2007-04-26

    申请号：US11580086

    申请日：2006-10-13

    申请人： Byung-Yong Choi ,  Choong-Ho Lee ,  Dong-Gun Park

    发明人： Byung-Yong Choi ,  Choong-Ho Lee ,  Dong-Gun Park

    IPC分类号： H01L29/792

    CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529

    摘要： A non-volatile memory device and a method of forming the same are provided. The non-volatile memory device may include a cell isolation pattern and a semiconductor pattern sequentially stacked on a predetermined or given region of a semiconductor substrate, a cell gate line on the semiconductor pattern and on a top surface of the semiconductor substrate on one side of the cell isolation pattern, a multi-layered trap insulation layer between the cell gate line and the semiconductor substrate, and the cell gate line and the semiconductor pattern, a first impurity diffusion layer in the semiconductor substrate on both sides of the cell gate line and a second impurity diffusion layer in the semiconductor pattern on both sides of the cell gate line.

    摘要翻译： 提供了一种非易失性存储器件及其形成方法。 非易失性存储器件可以包括依次层叠在半导体衬底的预定或给定区域上的单元隔离图案和半导体图案，半导体图案上的单元栅极线和半导体衬底的一侧的顶表面上的半导体图案 电池隔离图案，单元栅极线和半导体衬底之间的多层陷阱绝缘层，以及单元栅极线和半导体图案，在单元栅极线的两侧的半导体衬底中的第一杂质扩散层和 位于单元栅极线两侧的半导体图案中的第二杂质扩散层。

    Non-volatile memory device and methods of forming the same
    3.
    发明授权
    Non-volatile memory device and methods of forming the same 有权
    非易失性存储器件及其形成方法

    公开(公告)号：US07465985B2

    公开(公告)日：2008-12-16

    申请号：US11580086

    申请日：2006-10-13

    申请人： Byung-Yong Choi ,  Choong-Ho Lee ,  Dong-Gun Park

    发明人： Byung-Yong Choi ,  Choong-Ho Lee ,  Dong-Gun Park

    IPC分类号： H01L21/334

    CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529

    摘要： A non-volatile memory device and a method of forming the same are provided. The non-volatile memory device may include a cell isolation pattern and a semiconductor pattern sequentially stacked on a predetermined or given region of a semiconductor substrate, a cell gate line on the semiconductor pattern and on a top surface of the semiconductor substrate on one side of the cell isolation pattern, a multi-layered trap insulation layer between the cell gate line and the semiconductor substrate, and the cell gate line and the semiconductor pattern, a first impurity diffusion layer in the semiconductor substrate on both sides of the cell gate line and a second impurity diffusion layer in the semiconductor pattern on both sides of the cell gate line.

    摘要翻译： 提供了一种非易失性存储器件及其形成方法。 非易失性存储器件可以包括依次层叠在半导体衬底的预定或给定区域上的单元隔离图案和半导体图案，半导体图案上的单元栅极线和半导体衬底的一侧的顶表面上的半导体图案 电池隔离图案，单元栅极线和半导体衬底之间的多层陷阱绝缘层，以及单元栅极线和半导体图案，在单元栅极线的两侧的半导体衬底中的第一杂质扩散层和 位于单元栅极线两侧的半导体图案中的第二杂质扩散层。

    Method of fabricating a semiconductor device having self-aligned floating gate and related device
    4.
    发明授权
    Method of fabricating a semiconductor device having self-aligned floating gate and related device 有权
    制造具有自对准浮动栅极和相关器件的半导体器件的方法

    公开(公告)号：US07329580B2

    公开(公告)日：2008-02-12

    申请号：US11425205

    申请日：2006-06-20

    申请人： Byung-Yong Choi ,  Choong-Ho Lee ,  Tae-Yong Kim ,  Dong-Gun Park

    发明人： Byung-Yong Choi ,  Choong-Ho Lee ,  Tae-Yong Kim ,  Dong-Gun Park

    IPC分类号： H01L21/336

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66795 ,  H01L29/7851

    摘要： A semiconductor device such as a flash memory device having a self-aligned floating gate and a method of fabricating the same is provided. An embodiment of the device includes an isolation layer defining a fin body is formed in a semiconductor substrate. The fin body has a portion protruding above the isolation layer. A sacrificial pattern is formed on the isolation layer. The sacrificial pattern has an opening self-aligned with the protruding portion of the fin body. The protruding fin body is exposed in the opening. An insulated floating gate pattern is formed to fill the opening. The sacrificial pattern is then removed. An inter-gate dielectric layer covering the floating gate pattern is formed. A control gate conductive layer is formed over the inter-gate dielectric layer. The control gate conductive layer, the inter-gate dielectric layer, and the floating gate pattern are patterned to form a control gate electrode crossing the fin body as well as the insulated floating gate interposed between the control gate electrode and the fin body.

    摘要翻译： 提供了诸如具有自对准浮动栅极的闪速存储器件及其制造方法的半导体器件。 该器件的一个实施例包括在半导体衬底中形成限定翅片体的隔离层。 翅片本体具有突出在隔离层上方的部分。 在隔离层上形成牺牲图案。 牺牲图案具有与翅片体的突出部分自对准的开口。 突出的翅片体露出开口。 形成绝缘浮栅图形以填充开口。 然后去除牺牲图案。 形成覆盖浮栅图案的栅极间介电层。 在栅极间电介质层上形成控制栅极导电层。 对控制栅极导电层，栅极间电介质层和浮置栅极图案进行图案化以形成跨越鳍体的控制栅电极以及插在控制栅电极和鳍体之间的绝缘浮栅。

    Method of fabricating a semiconductor device having a single gate electrode corresponding to a pair of fin-type channel regions
    7.
    发明申请
    Method of fabricating a semiconductor device having a single gate electrode corresponding to a pair of fin-type channel regions 有权
    制造具有对应于一对鳍型沟道区的单个栅电极的半导体器件的方法

    公开(公告)号：US20070048934A1

    公开(公告)日：2007-03-01

    申请号：US11505335

    申请日：2006-08-17

    申请人： Suk-Pil Kim ,  Yoon-Dong Park ,  Won-Joo Kim ,  Dong-Gun Park ,  Eun-Suk Cho ,  Suk-Kang Sung ,  Byung-Yong Choi ,  Tae-Yong Kim ,  Choong-Ho Lee

    发明人： Suk-Pil Kim ,  Yoon-Dong Park ,  Won-Joo Kim ,  Dong-Gun Park ,  Eun-Suk Cho ,  Suk-Kang Sung ,  Byung-Yong Choi ,  Tae-Yong Kim ,  Choong-Ho Lee

    IPC分类号： H01L21/8242

    CPC分类号： H01L29/785 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/10873 ,  H01L27/10879 ,  H01L27/1159 ,  H01L27/2436 ,  H01L29/66795

    摘要： Provided are methods for fabricating semiconductor devices incorporating a fin-FET structure that provides body-bias control, exhibits some characteristic advantages associated with SOI structures, provides increased operating current and/or reduced contact resistance. The methods for fabricating semiconductor devices include forming insulating spacers on the sidewalls of a protruding portion of a first insulation film; forming a second trench by removing exposed regions of the semiconductor substrate using the insulating spacers as an etch mask, and thus forming fins in contact with and supported by the first insulation film. After forming the fins, a third insulation film is formed to fill the second trench and support the fins. A portion of the first insulation film is then removed to open a space between the fins in which additional structures including gate dielectrics, gate electrodes and additional contact, insulating and storage node structures may be formed.

    摘要翻译： 提供了制造具有提供体偏置控制的鳍式FET结构的半导体器件的方法，显示出与SOI结构相关的一些特征优点，提供增加的工作电流和/或降低的接触电阻。 制造半导体器件的方法包括在第一绝缘膜的突出部分的侧壁上形成绝缘间隔物; 通过使用绝缘间隔物作为蚀刻掩模去除半导体衬底的暴露区域，从而形成与第一绝缘膜接触并由第一绝缘膜支撑的鳍形成第二沟槽。 在形成翅片之后，形成第三绝缘膜以填充第二沟槽并支撑翅片。 然后去除第一绝缘膜的一部分以打开翅片之间的空间，其中可以形成包括栅极电介质，栅电极和附加接触，绝缘和存储节点结构的附加结构。