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    Method of forming fin field effect transistor using damascene process
    2.
    发明授权
    Method of forming fin field effect transistor using damascene process 有权
    使用镶嵌工艺形成翅片场效应晶体管的方法

    公开(公告)号：US07528022B2

    公开(公告)日：2009-05-05

    申请号：US11112818

    申请日：2005-04-21

    申请人： Young-Joon Ahn ,  Dong-Gun Park ,  Choong-Ho Lee ,  Hee-Soo Kang

    发明人： Young-Joon Ahn ,  Dong-Gun Park ,  Choong-Ho Lee ,  Hee-Soo Kang

    IPC分类号： H01L21/8234

    CPC分类号： H01L29/7851 ,  H01L21/26586 ,  H01L29/66818

    摘要： A method of forming a fin transistor using a damascene process is provided. A filling mold insulation pattern is recessed to expose an upper portion of a fin, and a mold layer is formed. The mold layer is patterned to form a groove crossing the fin and exposing a part of the upper portion of the fin. A gate electrode is formed to fill the groove with a gate insulation layer interposed between the fin and the gate electrode, and the mold layer is removed. Impurities are implanted through both sidewalls and a top surface of the upper portion of the fin disposed at opposite sides of a gate electrode to form a source/drain region.

    摘要翻译： 提供了一种使用镶嵌工艺形成鳍式晶体管的方法。 填充模具绝缘图案凹入以暴露翅片的上部，并且形成模具层。 图案化模具层以形成与散热片交叉的凹槽并暴露翅片上部的一部分。 形成栅电极，用插入翅片和栅电极之间的栅极绝缘层填充凹槽，并且去除模层。 通过设置在栅极电极的相对侧的翅片的上侧部分的两个侧壁和顶部表面注入杂质以形成源极/漏极区域。

    Method for forming a FinFET by a damascene process
    5.
    发明授权
    Method for forming a FinFET by a damascene process 有权
    通过镶嵌工艺形成FinFET的方法

    公开(公告)号：US07358142B2

    公开(公告)日：2008-04-15

    申请号：US11046623

    申请日：2005-01-28

    申请人： Hee-Soo Kang ,  Chul Lee ,  Tae-Yong Kim ,  Dong-Gun Park ,  Young-Joon Ahn ,  Choong-Ho Lee ,  Sang-Yeon Han

    发明人： Hee-Soo Kang ,  Chul Lee ,  Tae-Yong Kim ,  Dong-Gun Park ,  Young-Joon Ahn ,  Choong-Ho Lee ,  Sang-Yeon Han

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7851 ,  H01L29/66795

    摘要： A device isolation film and an active region are formed on a semiconductor substrate, using a first mask pattern to expose only a formation region of the device isolation film. Only the device isolation film is selectively etched by using the first mask pattern and a second mask pattern as an etch mask, to form a fin only on a gate formation region, the second mask pattern to expose only a gate electrode formation region. A gate insulation layer is formed on both sidewalls of the fin and a gate electrode covering the first mask pattern and the gate insulation layer is formed. Source and drain regions are formed on the remaining portion of the active region where the gate electrode was not formed. Gate electrode separation becomes adequate and manufacturing costs can be reduced.

    摘要翻译： 使用第一掩模图案在半导体衬底上形成器件隔离膜和有源区，仅暴露器件隔离膜的形成区域。 仅通过使用第一掩模图案和第二掩模图案作为蚀刻掩模来选择性地蚀刻器件隔离膜，仅在栅极形成区域形成鳍状物，第二掩模图案仅露出栅电极形成区域。 在翅片的两个侧壁上形成栅绝缘层，形成覆盖第一掩模图案的栅电极和栅极绝缘层。 源区和漏区形成在没有形成栅电极的有源区的剩余部分上。 栅电极分离变得足够，并且可以降低制造成本。

    Methods of forming integrated circuit devices having field effect transistors of different types in different device regions
    6.
    发明申请
    Methods of forming integrated circuit devices having field effect transistors of different types in different device regions 有权
    在不同的器件区域形成具有不同类型的场效应晶体管的集成电路器件的方法

    公开(公告)号：US20050239252A1

    公开(公告)日：2005-10-27

    申请号：US11110167

    申请日：2005-04-20

    申请人： Young-Joon Ahn ,  Dong-Gun Park ,  Choong-Ho Lee ,  Hee-Soo Kang

    发明人： Young-Joon Ahn ,  Dong-Gun Park ,  Choong-Ho Lee ,  Hee-Soo Kang

    IPC分类号： H01L27/088 ,  H01L21/336 ,  H01L21/8232 ,  H01L21/8234 ,  H01L21/8239 ,  H01L29/786 ,  H01L31/0328

    CPC分类号： H01L21/823412 ,  H01L21/823437 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/1052 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7851

    摘要： A method of forming an integrated circuit device includes forming a non-planar field-effect transistor in a cell array portion of a semiconductor substrate and forming a planar field-effect transistor in a peripheral circuit portion of the semiconductor substrate. The non-planar field-effect transistor may be selected from the group of a FinFET and a recessed gate FET. Dopants may be implanted into a channel region of the non-planar field-effect transistor, and a cell protection layer may be formed on the non-planar field-effect transistor. Then, dopants may be selectively implanted into a channel region of the planar field-effect transistor using the cell protection layer as a mask to block implanting of the dopants into the channel region of the non-planar field-effect transistor.

    摘要翻译： 形成集成电路器件的方法包括在半导体衬底的单元阵列部分中形成非平面场效应晶体管，并在半导体衬底的外围电路部分中形成平面场效应晶体管。 非平面场效应晶体管可以选自FinFET和凹入栅极FET。 可以将掺杂剂注入到非平面场效应晶体管的沟道区域中，并且可以在非平面场效应晶体管上形成电池保护层。 然后，可以使用电池保护层作为掩模将掺杂剂选择性地注入到平面场效应晶体管的沟道区域中，以阻止掺杂剂注入到非平面场效应晶体管的沟道区域中。

    Method for forming a FinFET by a damascene process
    7.
    发明申请
    Method for forming a FinFET by a damascene process 有权
    通过镶嵌工艺形成FinFET的方法

    公开(公告)号：US20050170593A1

    公开(公告)日：2005-08-04

    申请号：US11046623

    申请日：2005-01-28

    申请人： Hee-Soo Kang ,  Chul Lee ,  Tae-Yong Kim ,  Dong-Gun Park ,  Young-Joon Ahn ,  Choong-Ho Lee ,  Sang-Yeon Han

    发明人： Hee-Soo Kang ,  Chul Lee ,  Tae-Yong Kim ,  Dong-Gun Park ,  Young-Joon Ahn ,  Choong-Ho Lee ,  Sang-Yeon Han

    IPC分类号： H01L27/092 ,  H01L21/336 ,  H01L21/8228 ,  H01L29/786 ,  H01M8/00

    CPC分类号： H01L29/7851 ,  H01L29/66795

    摘要： A device isolation film and an active region are formed on a semiconductor substrate, using a first mask pattern to expose only a formation region of the device isolation film. Only the device isolation film is selectively etched by using the first mask pattern and a second mask pattern as an etch mask, to form a fin only on a gate formation region, the second mask pattern to expose only a gate electrode formation region. A gate insulation layer is formed on both sidewalls of the fin and a gate electrode covering the first mask pattern and the gate insulation layer is formed. Source and drain regions are formed on the remaining portion of the active region where the gate electrode was not formed. Gate electrode separation becomes adequate and manufacturing costs can be reduced.

    摘要翻译： 使用第一掩模图案在半导体衬底上形成器件隔离膜和有源区，仅暴露器件隔离膜的形成区域。 仅通过使用第一掩模图案和第二掩模图案作为蚀刻掩模来选择性地蚀刻器件隔离膜，仅在栅极形成区域形成鳍状物，第二掩模图案仅露出栅电极形成区域。 在翅片的两个侧壁上形成栅绝缘层，形成覆盖第一掩模图案的栅电极和栅极绝缘层。 源极和漏极区域形成在没有形成栅电极的有源区的剩余部分上。 栅电极分离变得足够，并且可以降低制造成本。

    Methods of forming integrated circuit devices having field effect transistors of different types in different device regions
    9.
    发明授权
    Methods of forming integrated circuit devices having field effect transistors of different types in different device regions 有权
    在不同的器件区域形成具有不同类型的场效应晶体管的集成电路器件的方法

    公开(公告)号：US07566619B2

    公开(公告)日：2009-07-28

    申请号：US11110167

    申请日：2005-04-20

    申请人： Young-Joon Ahn ,  Dong-Gun Park ,  Choong-Ho Lee ,  Hee-Soo Kang

    发明人： Young-Joon Ahn ,  Dong-Gun Park ,  Choong-Ho Lee ,  Hee-Soo Kang

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823412 ,  H01L21/823437 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/1052 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7851

    摘要： A method of forming an integrated circuit device includes forming a non-planar field-effect transistor in a cell array portion of a semiconductor substrate and forming a planar field-effect transistor in a peripheral circuit portion of the semiconductor substrate. The non-planar field-effect transistor may be selected from the group of a FinFET and a recessed gate FET. Dopants may be implanted into a channel region of the non-planar field-effect transistor, and a cell protection layer may be formed on the non-planar field-effect transistor. Then, dopants may be selectively implanted into a channel region of the planar field-effect transistor using the cell protection layer as a mask to block implanting of the dopants into the channel region of the non-planar field-effect transistor.

    摘要翻译： 形成集成电路器件的方法包括在半导体衬底的单元阵列部分中形成非平面场效应晶体管，并在半导体衬底的外围电路部分中形成平面场效应晶体管。 非平面场效应晶体管可以选自FinFET和凹入栅极FET。 可以将掺杂剂注入到非平面场效应晶体管的沟道区域中，并且可以在非平面场效应晶体管上形成电池保护层。 然后，可以使用电池保护层作为掩模将掺杂剂选择性地注入到平面场效应晶体管的沟道区域中，以阻止掺杂剂注入到非平面场效应晶体管的沟道区域中。