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    Memory device input buffer, related memory device, controller and system
    71.
    发明申请
    Memory device input buffer, related memory device, controller and system 失效
    存储器件输入缓冲器，相关存储器件，控制器和系统

    公开(公告)号：US20070070782A1

    公开(公告)日：2007-03-29

    申请号：US11515799

    申请日：2006-09-06

    Applicant: Dong-woo Lee ,  Jung-yong Choi ,  Jong-hyun Choi

    Inventor： Dong-woo Lee ,  Jung-yong Choi ,  Jong-hyun Choi

    IPC: G11C8/00

    CPC classification number: G11C8/06 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/109 ,  G11C7/225

    Abstract: Provided are an input buffer of a memory device, a memory controller, and a memory system making use thereof. The input buffer of a memory device is enabled or disabled in response to a first signal showing chip selection information and a second signal showing power down information, and the input buffer is enabled only when the second signal shows a non-power down mode and the first signal shows a chip selection state. The input buffer is at least one selected from the group consisting of a row address strobe input buffer, a column address strobe input buffer, and an address input buffer.

    Abstract translation: 提供了存储器件，存储器控制器和使用它的存储器系统的输入缓冲器。 响应于表示芯片选择信息的第一信号和表示掉电信息的第二信号，存储器件的输入缓冲器被使能或禁止，并且仅当第二信号显示非掉电模式时，输入缓冲器被使能，并且 第一信号显示芯片选择状态。 输入缓冲器是从由行地址选通输入缓冲器，列地址选通输入缓冲器和地址输入缓冲器组成的组中选择的至少一个。

    Packet addressing programmable dual port memory devices and related methods
    77.
    发明申请
    Packet addressing programmable dual port memory devices and related methods 有权
    分组寻址可编程双端口存储器件及相关方法

    公开(公告)号：US20050122824A1

    公开(公告)日：2005-06-09

    申请号：US10937519

    申请日：2004-09-09

    Applicant: Dong-Woo Lee

    Inventor： Dong-Woo Lee

    IPC: G11C8/06 ,  G11C11/34

    CPC classification number: G11C8/06

    Abstract: In a packet addressing method, one or more memory blocks are selected from a plurality of memory blocks and one or more data I/O pads are selected from a plurality of data I/O pads via which data input or output to/from the selected memory blocks are loaded, memory cell data output from the selected memory blocks are sequentially output to the selected data I/O pads, and data input to the selected data I/O pads are sequentially input to the selected memory blocks, so that read and write operations are independently accomplished in each of data I/O pads. The data I/O width can be adjusted according to the word length which is selectively set up, and power consumption can be reduced due to partial activation of the memory block.

    Abstract translation: 在分组寻址方法中，从多个存储器块中选择一个或多个存储器块，并且从多个数据I / O焊盘中选择一个或多个数据I / O焊盘，通过该数据I / O焊盘输入或输出数据 存储器块被加载，从所选择的存储器块输出的存储单元数据被顺序地输出到选择的数据I / O焊盘，并且输入到所选择的数据I / O焊盘的数据被顺序地输入到所选择的存储器块， 在每个数据I / O焊盘中独立地实现写入操作。 数据I / O宽度可以根据有选择地设置的字长进行调整，由于存储块的部分激活，能够降低功耗。

    Sense amplifier circuit for use in a semiconductor memory device
    78.
    发明授权
    Sense amplifier circuit for use in a semiconductor memory device 有权
    用于半导体存储器件的感测放大器电路

    公开(公告)号：US06381187B1

    公开(公告)日：2002-04-30

    申请号：US09671465

    申请日：2000-09-27

    Applicant: Dong-Woo Lee ,  Heung-Soo Im

    Inventor： Dong-Woo Lee ,  Heung-Soo Im

    IPC: G11C700

    CPC classification number: G11C7/062 ,  G11C7/067

    Abstract: Disclosed herein is a sense amplifier circuit which includes a first, a second and a third similar load transistors. The first and second load transistors supply a dummy data line with a current of the same amount to one another. Acting in a current mirror configuration, the third load transistor supplies a data line with a current equaling the total current supplied by the first and second load transistors. A dummy memory cell is composed of the same transistor as an on-state memory cell. According to this sense amplifier structure, it is very easy to obtain a dummy cell current which has an intermediate value consistently between an on cell current and an off cell current of the memory cell, which are supplied from the third load transistor to the data line. The improved intermediate value yields a reliable readout of the memory cell.

    Abstract translation: 这里公开了一种读出放大器电路，其包括第一，第二和第三类似的负载晶体管。 第一和第二负载晶体管提供具有彼此相同量的电流的虚拟数据线。 作为电流镜配置，第三负载晶体管以等于由第一和第二负载晶体管提供的总电流的电流提供数据线。 虚拟存储单元由与状态存储单元相同的晶体管组成。 根据这种感测放大器结构，很容易获得在从第三负载晶体管提供到数据线的存储单元的导通单元电流和截止单元电流之间具有一致的中间值的虚设单元电流 。 改进的中间值产生可靠的存储单元的读出。

    Device and method for controlling distortion characteristic of predistorter
    79.
    发明授权
    Device and method for controlling distortion characteristic of predistorter 失效
    用于控制预失真器失真特性的装置和方法

    公开(公告)号：US06246865B1

    公开(公告)日：2001-06-12

    申请号：US08789232

    申请日：1997-02-04

    Applicant: Dong-Woo Lee

    Inventor： Dong-Woo Lee

    IPC: H03C162

    CPC classification number: H04B1/62 ,  H01Q11/12 ,  H03D7/00

    Abstract: A device and a method for meeting the distortion characteristic of a predistorter in accordance with the distortion characteristic of an output amplifier in a transmitter. The device controls the non-linear distortion characteristic of a predistorter in a radio communication transmitter which includes the predistorter for beforehand generating the non-linear distortion characteristic in opposition to non-linear distortion characteristics arising in an output amplifier, and up-converter for converting an output frequency of the predistorter into a radio frequency bandpass and outputting the converted frequency to the output amplifier. The device includes: a monitoring unit for monitoring the output level of the output amplifier; a storing unit for beforehand storing the non-linear distortion characteristics of the predistorter as digital data; a distortion controller for outputting and controlling given non-linear distortion characteristic digital data stored in the storing unit in correspondence with the output level of the monitoring unit; and a digital/analog converter for converting the non-linear distortion characteristic digital data outputted by the distortion controller into an analog signal and providing the converted data to the predistorter.

    Abstract translation: 根据发射机中的输出放大器的失真特性来满足预失真器的失真特性的装置和方法。 该装置控制无线电通信发射机中的预失真器的非线性失真特性，该无线通信发射机包括用于与输出放大器中产生的非线性失真特性相反的事先产生非线性失真特性的预失真器，以及用于转换的上变频器 将预失真器的输出频率转换成射频带通，并将转换的频率输出到输出放大器。 该装置包括：监控单元，用于监视输出放大器的输出电平; 存储单元，用于预先将所述预失真器的非线性失真特性存储为数字数据; 失真控制器，用于根据监视单元的输出电平输出和控制存储在存储单元中的给定非线性失真特性数字数据; 以及数字/模拟转换器，用于将由失真控制器输出的非线性失真特性数字数据转换为模拟信号，并将转换的数据提供给预失真器。

    Method for exploring useful genetic resources through bulk metagenome analysis and use thereof
    80.
    发明授权
    Method for exploring useful genetic resources through bulk metagenome analysis and use thereof 有权

    公开(公告)号：US11345959B2

    公开(公告)日：2022-05-31

    申请号：US15756441

    申请日：2016-06-24

    Applicant: Dong Woo Lee

    Inventor： Dong Woo Lee ,  Yong Jik Lee ,  Sang Jae Lee ,  Han Seung Lee

    IPC: C12Q1/6869 ,  C12Q1/6806 ,  C12Q1/6844 ,  C12Q1/6888

    Abstract: Provided is a method for analyzing metagenomic information using a degenerate primer which can be applied for quickly determining the utility value of a massive amount of metagenome samples. In particular, the superfamily-specific degenerate primer of the present invention is used to quickly detect the presence or absence of the genetic information of the target peptides in the metagenome by a simple method, thereby collecting a large amount of useful peptide resource information from various metagenome samples at high speed. Further, the present invention may be used for screening new peptide genes by designing and producing superfamily-specific degenerate primers of new target peptides based on the method of the present invention. In addition, the method of the present invention can be applied not only to enzymes but also to studies related to polypeptides, oligopeptides, antibiotic resistance genes, antimicrobial peptides, antifungal peptides, oligopeptides, markers, or single-nucleotide polymorphism (SNP).

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