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    Process for preparing photosensitive outer layer
    72.
    发明授权
    Process for preparing photosensitive outer layer 有权
    光敏外层制备方法

    公开(公告)号：US08017294B2

    公开(公告)日：2011-09-13

    申请号：US11900679

    申请日：2007-09-13

    Applicant: John F. Yanus ,  Kenny-Tuan Dinh ,  Jin Wu ,  Dale S. Renfer

    Inventor： John F. Yanus ,  Kenny-Tuan Dinh ,  Jin Wu ,  Dale S. Renfer

    IPC: G03G5/147

    CPC classification number: G03G5/0571 ,  G03G5/0575 ,  G03G5/0589 ,  G03G5/0592 ,  G03G5/071 ,  G03G5/075 ,  G03G5/105 ,  G03G5/14747 ,  G03G5/14765 ,  G03G5/14769 ,  G03G5/14786 ,  G03G5/14791

    Abstract: The presently disclosed embodiments are directed to an improved overcoat for an imaging member having a substrate, a charge transport layer, and an overcoat positioned on the charge transport layer, and a process for making the same including combining a resin having a reactive group selected from the group consisting of hydroxyl, carboxylic acid and amide groups, a melamine formaldehyde crosslinking agent, a crosslinkable fluoro additive, an acid catalyst, and a crosslinkable, alcohol-soluble charge transport molecule to form an overcoat solution, and subsequently providing the overcoat solution onto the charge transport layer to form an overcoat layer.

    Abstract translation: 目前公开的实施例涉及用于具有衬底，电荷传输层和位于电荷传输层上的外涂层的成像构件的改进外涂层，以及制备该成膜构件的方法，包括将具有反应性基团的树脂 由羟基，羧酸和酰胺基组成的组，三聚氰胺甲醛交联剂，可交联的氟添加剂，酸催化剂和可交联的醇可溶电荷转运分子，以形成外涂层溶液，随后将外涂层溶液 电荷输送层以形成外涂层。

    Tris(enylaryl)amine containing photoconductors
    76.
    发明授权
    Tris(enylaryl)amine containing photoconductors 有权
    含有感光体的三（烯基芳基）胺

    公开(公告)号：US08007971B2

    公开(公告)日：2011-08-30

    申请号：US12164549

    申请日：2008-06-30

    Applicant: Jin Wu

    Inventor： Jin Wu

    IPC: G03G5/00

    CPC classification number: G03G5/0575 ,  G03G5/0535 ,  G03G5/14721 ,  G03G5/14769 ,  Y10S430/103

    Abstract: A photoconductor that includes, for example, a supporting substrate, a photogenerating layer, and a tris(enylaryl)amine containing charge transport layer.

    Abstract translation: 光电导体，其包括例如支撑基板，光生成层和含有三（烯基芳基）胺的电荷输送层。

    Ferrocene containing photoconductors
    77.
    发明授权
    Ferrocene containing photoconductors 有权
    含二茂铁的感光体

    公开(公告)号：US08003289B2

    公开(公告)日：2011-08-23

    申请号：US12129965

    申请日：2008-05-30

    Applicant: Jin Wu

    Inventor： Jin Wu

    IPC: G03G5/047

    CPC classification number: G03G5/0614 ,  G03G5/0601 ,  G03G5/0607 ,  G03G5/0662 ,  G03G5/0696

    Abstract: A photoconductor that includes, for example, a supporting substrate, a photogenerating layer, and at least one charge transport layer comprised of at least one charge transport component, and wherein at least one of the photogenerating layer and charge transport layer contains a ferrocene.

    Abstract translation: 一种光电导体，其包括例如支撑衬底，光生成层和至少一个由至少一个电荷传输组分组成的电荷传输层，并且其中光生成层和电荷传输层中的至少一个含有二茂铁。

    METHOD FOR THINNING A WAFER
    78.
    发明申请
    METHOD FOR THINNING A WAFER 有权
    薄膜方法

    公开(公告)号：US20110198721A1

    公开(公告)日：2011-08-18

    申请号：US12704695

    申请日：2010-02-12

    Applicant: Ku-Feng YANG ,  Weng-Jin Wu ,  Hsin-Hsien Lu ,  Chia-Lin Yu ,  Chu-Sung Shih ,  Fu-Chi Hsu ,  Shau-Lin Shue

    Inventor： Ku-Feng YANG ,  Weng-Jin Wu ,  Hsin-Hsien Lu ,  Chia-Lin Yu ,  Chu-Sung Shih ,  Fu-Chi Hsu ,  Shau-Lin Shue

    IPC: H01L23/544 ,  H01L21/304 ,  H01L21/306 ,  H01L29/06 ,  H01L21/768 ,  H01L23/48

    CPC classification number: H01L21/76898 ,  H01L2224/02372

    Abstract: A method for thinning a wafer is provided. In one embodiment, a wafer is provided having a plurality of semiconductor chips, the wafer having a first side and a second side opposite the first side, wherein each of the chips includes a set of through silicon vias (TSVs), each of the TSVs substantially sealed by a liner layer and a barrier layer. A wafer carrier is provided for attaching to the second side of the wafer. The first side of the wafer is thinned and thereafer recessed to partially expose portions of the liner layers, barrier layers and the TSVs protruding from the wafer. An isolation layer is deposited over the first side of the wafer and the top portions of the liner layers, barrier layers and the TSVs. Thereafter, an insulation layer is deposited over the isolation layer. The insulation layer is then planarized to expose top portions of the TSVs. A dielectric layer is deposited over the planarized first side of the wafer. One or more electrical contacts are formed in the dielectric layer for electrical connection to the exposed one or more TSVs.

    Abstract translation: 提供了一种用于薄化晶片的方法。 在一个实施例中，提供具有多个半导体芯片的晶片，晶片具有第一侧和与第一侧相对的第二侧，其中每个芯片包括一组穿通硅通孔（TSV），每个TSV 基本上被衬垫层和阻挡层密封。 提供晶片载体以附接到晶片的第二侧。 晶片的第一侧变薄并且凹陷以部分地暴露衬里层，阻挡层和从晶片突出的TSV的部分。 隔离层沉积在晶片的第一侧和衬垫层，阻挡层和TSV的顶部之上。 此后，绝缘层沉积在隔离层上。 然后将绝缘层平坦化以暴露TSV的顶部。 电介质层沉积在晶片的平坦化第一侧上。 在电介质层中形成一个或多个电触头，用于与暴露的一个或多个TSV电连接。

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