摘要:
Disclosed is a design structure for an apparatus for a task based debugger (transaction-event-job-trigger). More specifically, an integrated event monitor for a SOC comprises functional cores each having a functional debug logic element. The cores are connected to an interconnect structure that links the functional debug logic elements. Each functional debug logic element is specifically dedicated to a function of its corresponding core, wherein the functional debug logic elements generate a table of function-specific system events. The system events are function-specific with respect to an associated core, wherein the system events include transaction events, controller events, processor events, interconnect structure arbiter events, interconnect interface core events, high speed serial link core events, and/or codec events.
摘要:
An optical transmission method. Signal transmissions between cores of an integrated circuit are performed. Each signal transmission is between two cores of a different pair of cores of the integrated circuit. Each signal transmission includes transmission of an optical signal in the visible or infrared portion of the electromagnetic spectrum at a wavelength that is specific to each different pair of cores and is a different wavelength for each different pair of cores. There is no overhead for decoding or arbitration in preforming the signal transmissions that would otherwise exist if a same wavelength for the optical signals were permitted for pairs of cores of the different pairs of cores.
摘要:
A structure and associated method of processing data on a semi-conductor device comprising an input island, a processing island, and an output island formed on the semiconductor device. The input island is adapted to accept a specified amount of data and enable a means for providing a first specified voltage for powering the processing island after accepting the specified amount of data. The processing island is adapted to receive and process the specified amount of data from the input island upon powering the processing island by the first specified voltage. The output island is adapted to be powered by a second specified voltage. The processing island is further adapted to transmit the processed data to the output island upon said powering by the second specified voltage. The first specified voltage is adapted to be disabled thereby removing power from processing island upon completion of transmission of the processed data to the output island.
摘要:
An integrated circuit, method and system providing finer granularity dynamic voltage control without performance loss. The invention provides a means for dynamically changing a voltage level of at least one stage on a critical path for a particular cycle. In this way, optimum voltages can be provided to the stages for the given expectation.
摘要:
According to the preferred embodiment, a device and method for reducing power consumption by reducing unneeded node toggling is provided. The preferred embodiment reduces unneeded toggling that commonly occurs in many types of logic circuits. The preferred embodiment reduces unneeded node toggling in a circuit by holding a portion of the device at the previous output until the all the inputs have stabilized to their final value during each clock cycle. This reduces power consumption in the device that would normally occur due to unnecessary node toggling.
摘要:
An apparatus and method controlling power consumption in portable personal computers by dynamically allocating power to the system logic. Expected total power consumption is calculated and compared to an optimum power efficiency value. The expected power consumption values for each execution unit are stored in a look-up table in actual or compressed form. If the expected total power consumption value exceeds the power efficiency value, selected execution units are made inactive. Conversely, if the power efficiency value exceeds the expected total power consumption value, execution unit functions are added in order to maintain a level current demand on the battery.
摘要:
An integrated circuit such as an ASIC device having partitioned functional units with independent threshold voltage control. A first partition is always operated in a normal mode, while subsequent partitions are maintained in a standby mode until a transition is detected at the input of the first partition. The subsequent partitions are switched to the normal mode by lowering the body voltage applied to the devices with each partition. A pulse stretcher is used to keep a partition in a normal mode for a predetermined period of time after the transition is detected.
摘要:
Disclosed are embodiments of on-chip identification circuitry. In one embodiment, pairs of conductors (e.g., metal pads, vias, lines) are formed within one or more metallization layers. The distance between the conductors in each pair is predetermined so that, given known across chip line variations, there is a random chance (i.e., an approximately 50/50 chance) of a short. In another embodiment different masks form first conductors (e.g., metal lines separated by varying distances and having different widths) and second conductors (e.g., metal vias separated by varying distances and having equal widths). The first and second conductors alternate across the chip. Due to the different separation distances and widths of the first conductors, the different separation distances of the second conductors and, random mask alignment variations, each first conductor can short to up to two second conductors. In each embodiment the resulting pattern of shorts and opens, can be used as an on-chip identifier or private key.
摘要:
A MEMS component is monitored to determine its status. Sensors are deployed to sense the MEMS component and produce detection signals that are analyzed to determine the MEMS component state. An indicator device alerts a user of the status, particularly if the MEMS component has failed. Additionally, the MEMS component monitoring system may be practiced as a design structure encoded on computer readable storage media as part of a circuit design system.
摘要:
A method and structure to optimize computational efficiency in a low-power environment. A design structure is embodied in a machine readable medium used in a design process. The design structure includes a component to determine an optimal point for maximizing computational efficiency in a low-power environment, and a component to selectively control operation of at least one processing unit of a plurality of processing units in accordance with the determined optimal point. The design structure further includes at least one of a component for controlling a frequency of a clock signal transmitted to the at least one processing unit in accordance with the determined optimal point, and a component for determining a present power available.