中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

167 records (took 0.036 seconds)

    SEMICONDUCTOR DEVICE, SEMICONDUCTOR WAFER, AND METHODS OF MANUFACTURING THE SAME
    71.
    发明申请
    SEMICONDUCTOR DEVICE, SEMICONDUCTOR WAFER, AND METHODS OF MANUFACTURING THE SAME 审中-公开
    半导体器件，半导体器件及其制造方法

    公开(公告)号：US20120313172A1

    公开(公告)日：2012-12-13

    申请号：US13489128

    申请日：2012-06-05

    Applicant: Masaharu MATSUDAIRA ,  Toshiharu Nagumo ,  Hiroshi Takeda ,  Kiyoshi Takeuchi

    Inventor： Masaharu MATSUDAIRA ,  Toshiharu Nagumo ,  Hiroshi Takeda ,  Kiyoshi Takeuchi

    IPC: H01L27/088 ,  H01L21/762 ,  H01L21/20 ,  H01L29/02

    CPC classification number: H01L27/1203 ,  H01L21/76254 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1207 ,  H01L29/78648

    Abstract: This invention is to provide a semiconductor device having a reduced variation in the transistor characteristics. The semiconductor device has a SOI substrate, a first element isolation insulating layer, first and second conductivity type transistors, and first and second back gate contacts. The SOI substrate has a semiconductor substrate having first and second conductivity type layers, an insulating layer, and a semiconductor layer. The first element isolation insulating layer is buried in the SOI substrate, has a lower end reaching the first conductivity type layer, and isolates a first element region from a second element region. The first and second conductivity type transistors are located in the first and second element regions, respectively, and have respective channel regions formed in the semiconductor layer. The first and second back gate contacts are coupled to the second conductivity type layers in the first and second element regions, respectively.

    Abstract translation: 本发明提供一种具有减小的晶体管特性变化的半导体器件。 半导体器件具有SOI衬底，第一元件隔离绝缘层，第一和第二导电型晶体管以及第一和第二后栅极触点。 SOI衬底具有具有第一和第二导电类型层，绝缘层和半导体层的半导体衬底。 第一元件隔离绝缘层被埋在SOI衬底中，具有到达第一导电类型层的下端，并且将第一元件区域与第二元件区域隔离。 第一和第二导电类型晶体管分别位于第一和第二元件区域中，并且在半导体层中形成有各自的沟道区。 第一和第二背栅极触点分别耦合到第一和第二元件区域中的第二导电类型层。

    Manufacturing process of fin-type field effect transistor and semiconductor
    74.
    发明授权
    Manufacturing process of fin-type field effect transistor and semiconductor 失效
    鳍型场效应晶体管和半导体的制造工艺

    公开(公告)号：US08247294B2

    公开(公告)日：2012-08-21

    申请号：US12946034

    申请日：2010-11-15

    Applicant: Kiyoshi Takeuchi ,  Katsuhiko Tanaka

    Inventor： Kiyoshi Takeuchi ,  Katsuhiko Tanaka

    IPC: H01L21/336

    CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/785

    Abstract: A constant distance can be maintained between source/drain regions without providing a gate side wall by forming a gate electrode including an eaves structure, and a uniform dopant concentration is kept within a semiconductor by ion implantation. As a result, a FinFET excellent in element properties and operation properties can be obtained. A field effect transistor, wherein a gate structure body is a protrusion that protrudes toward source and drain regions sides in a channel length direction and has a channel length direction width larger than that of the part adjacent to the insulating film in a gate electrode, and the protrusion includes an eaves structure formed by the protrusion that extends in a gate electrode extending direction on the top surface of the semiconductor layer.

    Abstract translation: 通过形成包括屋顶结构的栅极电极，可以在源/漏区之间保持恒定的距离，而不需要提供栅极侧壁，并且通过离子注入将均匀的掺杂剂浓度保持在半导体内。 结果，可以获得元件性能和操作性能优异的FinFET。 一种场效应晶体管，其中栅极结构体是在沟道长度方向上朝向源极和漏极区域侧突出的突起，并且沟道长度方向宽度大于栅电极中与绝缘膜相邻的部分的沟道长度方向宽度;以及 突起包括由半导体层的顶表面上沿栅电极延伸方向延伸的突起形成的檐结构。

    INFORMATION STORAGE DEVICE AND TEST METHOD THEREFOR
    75.
    发明申请
    INFORMATION STORAGE DEVICE AND TEST METHOD THEREFOR 有权
    信息存储设备及其测试方法

    公开(公告)号：US20110179321A1

    公开(公告)日：2011-07-21

    申请号：US13010363

    申请日：2011-01-20

    Applicant: Kiyoshi TAKEUCHI

    Inventor： Kiyoshi TAKEUCHI

    IPC: G11C29/08 ,  G06F11/26

    CPC classification number: G11C29/50 ,  G11C11/41 ,  G11C29/06 ,  G11C29/12005 ,  G11C2029/5004

    Abstract: A method of testing the operational margin of an information storage device having marked random variations, and an information storage device having the function of self-diagnosing the operational margin, are provided. The test method includes testing an information storage device including a plurality of memory bits as the test condition is set so as to be outside a range of conditions that may be presupposed in real use of the information storage device and of counting the number of memory bits that fail in operation. The test method also includes verifying the size of the operational margin of the information storage device based on the count value. The test condition is made severe and the reference value is set to a fairly large value to enable the operational margin against the noise to be tested highly accurately.

    Abstract translation: 提供一种测试具有标记的随机变化的信息存储设备的操作余量的方法，以及具有自诊断操作余量功能的信息存储设备。 测试方法包括测试包括多个存储器位的信息存储设备，因为测试条件被设置为处于实际使用信息存储设备的前提条件范围内，并且对存储器位数进行计数 失败了。 测试方法还包括基于计数值验证信息存储设备的操作余量的大小。 测试条件变得严重，参考值被设置为相当大的值，以使得能够高精度地测试噪声的操作余量。

    MANUFACTURING PROCESS OF FIN-TYPE FIELD EFFECT TRANSISTOR AND SEMICONDUCTOR
    76.
    发明申请
    MANUFACTURING PROCESS OF FIN-TYPE FIELD EFFECT TRANSISTOR AND SEMICONDUCTOR 失效
    微型场效应晶体管和半导体的制造工艺

    公开(公告)号：US20110059584A1

    公开(公告)日：2011-03-10

    申请号：US12946034

    申请日：2010-11-15

    Applicant: Kiyoshi TAKEUCHI ,  Katsuhiko Tanaka

    Inventor： Kiyoshi TAKEUCHI ,  Katsuhiko Tanaka

    IPC: H01L21/8238 ,  H01L21/336

    CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/785

    Abstract: A constant distance can be maintained between source/drain regions without providing a gate side wall by forming a gate electrode including an eaves structure, and a uniform dopant concentration is kept within a semiconductor by ion implantation. As a result, a FinFET excellent in element properties and operation properties can be obtained. A field effect transistor, wherein a gate structure body is a protrusion that protrudes toward source and drain regions sides in a channel length direction and has a channel length direction width larger than that of the part adjacent to the insulating film in a gate electrode, and the protrusion includes an eaves structure formed by the protrusion that extends in a gate electrode extending direction on the top surface of the semiconductor layer.

    Abstract translation: 通过形成包括屋顶结构的栅极电极，可以在源/漏区之间保持恒定的距离，而不需要提供栅极侧壁，并且通过离子注入将均匀的掺杂剂浓度保持在半导体内。 结果，可以获得元件性能和操作性能优异的FinFET。 一种场效应晶体管，其中栅极结构体是在沟道长度方向上朝向源极和漏极区域侧突出的突起，并且沟道长度方向宽度大于栅电极中与绝缘膜相邻的部分的沟道长度方向宽度;以及 突起包括由半导体层的顶表面上沿栅电极延伸方向延伸的突起形成的檐结构。

    DOUBLE RACK AND PINION OSCILLATING DEVICE
    77.
    发明申请
    DOUBLE RACK AND PINION OSCILLATING DEVICE 有权
    双机架和PINION振荡器

    公开(公告)号：US20100064834A1

    公开(公告)日：2010-03-18

    申请号：US12553376

    申请日：2009-09-03

    Applicant: Kiyoshi TAKEUCHI ,  Mitsunori Magaribuchi ,  Kazuhiro Shinohara

    Inventor： Kiyoshi TAKEUCHI ,  Mitsunori Magaribuchi ,  Kazuhiro Shinohara

    IPC: F16H1/04

    CPC classification number: F15B15/065 ,  F15B15/1433 ,  F15B15/149

    Abstract: A plurality of ring-shaped sealing members are spaced from each other on the outer periphery of each of first and second end caps that seal openings of first and second cylinder holes. Ring-shaped flow paths are formed between adjacent ring-shaped sealing members. Parts of air flow paths that supply and discharge compressed air to and from pressure chambers of the cylinder holes are formed by the ring-shaped flow paths.

    Abstract translation: 多个环形密封构件在第一和第二端盖的每个的外周上彼此间隔开，从而密封第一和第二气缸孔的开口。 在相邻的环形密封件之间形成环形流路。 通过环形流路形成向气缸孔的压力室供给和排出压缩空气的空气流路的一部分。

    DISEASE NAME INPUT SUPPORT PROGRAM, METHOD AND APPARATUS
    78.
    发明申请
    DISEASE NAME INPUT SUPPORT PROGRAM, METHOD AND APPARATUS 审中-公开
    疾病名称输入支持程序，方法和设备

    公开(公告)号：US20090287663A1

    公开(公告)日：2009-11-19

    申请号：US12504347

    申请日：2009-07-16

    Applicant: Kiyoshi TAKEUCHI

    Inventor： Kiyoshi TAKEUCHI

    IPC: G06F17/30

    CPC classification number: G06F19/324 ,  G16H10/60 ,  G16H50/20

    Abstract: This disease name input support method includes: obtaining type data of a schema selected by a user and identification data of a region on the schema, which is identified by the user, and storing obtained data into a storage device; searching a disease name knowledge storage device storing an inputted disease name in association with the type data of the schema and the identification data of the region on the schema by using the obtained type data of the schema and the obtained identification data of the region on the schema, which are stored in the storage device, to extract a corresponding disease name; and presenting the extracted corresponding disease name as an input candidate disease name to the user.

    Abstract translation: 该疾病名称输入支援方法包括：获取由用户选择的模式的类型数据和由用户识别的模式上的区域的识别数据，并将取得的数据存储到存储装置中; 通过使用所获得的模式的类型数据和所获得的区域的识别数据来搜索在模式上与模式的类型数据和区域的识别数据相关联地存储输入的疾病名称的疾病名称知识存储装置， 模式，存储在存储设备中，以提取相应的疾病名称; 并将所提取的相应疾病名称作为输入候选疾病名称呈现给用户。

Patent Agency Ranking