公开(公告)号：US08514627B2

公开(公告)日：2013-08-20

申请号：US13235389

申请日：2011-09-18

申请人： Kiyotaro Itagaki ,  Masaru Kito ,  Ryu Ogiwara ,  Hitoshi Iwai

发明人： Kiyotaro Itagaki ,  Masaru Kito ,  Ryu Ogiwara ,  Hitoshi Iwai

IPC分类号： G11C16/04

CPC分类号： G11C16/14 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/344 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

摘要： A control circuit is configured to execute an erasing operation on a selected cell unit in a selected memory block. In the erasing operation, the control circuit raises the voltage of the bodies of the first memory transistors included in the selected cell unit to a first voltage, sets the voltage of the bodies of the first memory transistors included in the non-selected cell unit to a second voltage lower than the first voltage, and applies a third voltage equal to or lower than the second voltage to the gates of the first memory transistors included in the selected cell unit and the non-selected cell unit.

摘要翻译： 控制电路被配置为对选择的存储块中的所选择的单元单元执行擦除操作。 在擦除操作中，控制电路将包括在所选择的单元单元中的第一存储晶体管的主体的电压升高到第一电压，将未选择的单元单元中包括的第一存储晶体管的主体的电压设置为 第二电压低于第一电压，并将等于或低于第二电压的第三电压施加到所选择的单元单元和未选择的单元单元中包括的第一存储晶体管的栅极。

公开(公告)号：US20120057405A1

公开(公告)日：2012-03-08

申请号：US13196417

申请日：2011-08-02

申请人： Ryu Ogiwara ,  Hitoshi Iwai ,  Kiyotaro Itagaki

发明人： Ryu Ogiwara ,  Hitoshi Iwai ,  Kiyotaro Itagaki

IPC分类号： G11C16/10 ,  G11C16/04

CPC分类号： G11C16/30 ,  H01L27/0688 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582

摘要： According to one embodiment, a semiconductor memory device comprises a cell array, voltage generation circuits, and a control circuit. The cell array comprises memory cell strings. The voltage generation circuits are arranged below the cell array. Each of the memory cell strings comprises a semiconductor layer, control gates, and memory cell transistors. The semiconductor layer comprises a pair of pillar portions, and a connecting portion. The control gates intersect the pillar portion. The memory cell transistors are formed at intersections of the pillar portion and the control gates. In a write operation and a read operation, the control circuit does not drive voltage generation circuits which give noise to memory cell strings as a write target and a read target, and drives voltage generation circuits which do not give noise to the memory cell strings as the write target and the read target.

摘要翻译： 根据一个实施例，半导体存储器件包括单元阵列，电压产生电路和控制电路。 单元阵列包括存储单元串。 电压产生电路布置在电池阵列的下方。 每个存储单元串包括半导体层，控制栅极和存储单元晶体管。 半导体层包括一对柱部和连接部。 控制门与柱部相交。 存储单元晶体管形成在柱部分和控制栅极的交点处。 在写入操作和读取操作中，控制电路不驱动对作为写入目标和读取目标的存储单元串产生噪声的电压产生电路，并且驱动不对存储器单元串产生噪声的电压产生电路作为 写目标和读目标。

公开(公告)号：US08045358B2

公开(公告)日：2011-10-25

申请号：US12635590

申请日：2009-12-10

申请人： Ryu Ogiwara ,  Daisaburo Takashima

发明人： Ryu Ogiwara ,  Daisaburo Takashima

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory device including: a memory cell array including: memory cell blocks each having series-connected memory cells; wordlines; and a bitline pair connected to the memory cell blocks, one functioning as a readout bitline, the other one functioning as a reference bitline; an amplification circuit connected to the bitline pair to amplify a signal difference therebetween; and a reference voltage generation circuit including: a dummy memory cell block that has the same configuration as the memory cell block, that has one terminal connected to a first dummy plate line and that has the other terminal connected to the reference bitline; and a paraelectric capacitor that has one terminal connected to a second dummy plate line and that has the other terminal connected to the reference bitline.

摘要翻译： 根据本发明的一个方面，提供了一种非易失性半导体存储器件，包括：存储单元阵列，包括：具有串联存储单元的存储单元块; 字线 以及连接到存储单元块的位线对，一个用作读出位线，另一个用作参考位线; 连接到所述位线对的放大电路，以放大其间的信号差; 以及参考电压产生电路，包括：具有与所述存储单元块相同配置的虚拟存储单元块，其具有连接到第一虚设板线并且具有连接到所述参考位线的另一个端子的一个端子; 以及具有一个端子连接到第二虚拟板线并且另一个端子连接到参考位线的顺电电容器。

公开(公告)号：US07852142B2

公开(公告)日：2010-12-14

申请号：US12250121

申请日：2008-10-13

申请人： Ryu Ogiwara ,  Daisaburo Takashima

发明人： Ryu Ogiwara ,  Daisaburo Takashima

IPC分类号： G05F1/10

CPC分类号： G05F3/30

摘要： An amplifying circuit receives an output from a comparator. The output is provided to each gate of first, second and third transistors. First and second resistors are connected in series. The first and second resistors and a first diode are connected to a drain of the first transistor. Second diodes are connected in parallel. The second diodes are connected to one end of a third resistor. The other end of the third resistor is connected to a drain of the second transistor. Fourth and fifth resistors are connected in series. One end of the fourth resistor is connected to the drain of the second transistor. The comparator receives first and second feedback voltages respectively obtained from a connection node between the first and second resistors and a connection node between the fourth and fifth resistors. A drain of the third transistor outputs a reference voltage.

摘要翻译： 放大电路接收比较器的输出。 输出提供给第一，第二和第三晶体管的每个栅极。 第一和第二电阻串联连接。 第一和第二电阻器和第一二极管连接到第一晶体管的漏极。 第二个二极管并联连接。 第二二极管连接到第三电阻器的一端。 第三电阻器的另一端连接到第二晶体管的漏极。 第四和第五电阻串联连接。 第四电阻器的一端连接到第二晶体管的漏极。 比较器接收分别从第一和第二电阻器之间的连接节点获得的第一和第二反馈电压以及第四和第五电阻器之间的连接节点。 第三晶体管的漏极输出参考电压。

公开(公告)号：US20100149850A1

公开(公告)日：2010-06-17

申请号：US12635590

申请日：2009-12-10

申请人： Ryu OGIWARA ,  Daisaburo TAKASHIMA

发明人： Ryu OGIWARA ,  Daisaburo TAKASHIMA

IPC分类号： G11C11/22 ,  G11C7/06 ,  G11C5/06

CPC分类号： G11C11/22

摘要： According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory device including: a memory cell array including: memory cell blocks each having series-connected memory cells; wordlines; and a bitline pair connected to the memory cell blocks, one functioning as a readout bitline, the other one functioning as a reference bitline; an amplification circuit connected to the bitline pair to amplify a signal difference therebetween; and a reference voltage generation circuit including: a dummy memory cell block that has the same configuration as the memory cell block, that has one terminal connected to a first dummy plate line and that has the other terminal connected to the reference bitline; and a paraelectric capacitor that has one terminal connected to a second dummy plate line and that has the other terminal connected to the reference bitline.

摘要翻译： 根据本发明的一个方面，提供了一种非易失性半导体存储器件，包括：存储单元阵列，包括：具有串联存储单元的存储单元块; 字线 以及连接到存储单元块的位线对，一个用作读出位线，另一个用作参考位线; 连接到所述位线对的放大电路，以放大其间的信号差; 以及参考电压产生电路，包括：具有与所述存储单元块相同配置的虚拟存储单元块，其具有连接到第一虚设板线并且具有连接到所述参考位线的另一个端子的一个端子; 以及具有一个端子连接到第二虚拟板线并且另一个端子连接到参考位线的顺电电容器。

公开(公告)号：US20100090727A1

公开(公告)日：2010-04-15

申请号：US12563980

申请日：2009-09-21

申请人： Ryu Ogiwara ,  Daisaburo Takashima

发明人： Ryu Ogiwara ,  Daisaburo Takashima

IPC分类号： H03K5/153 ,  H03K5/00

CPC分类号： H03K17/223 ,  H03K5/153

摘要： A voltage detection circuit of the present invention includes an NMOS transistor diode-connected, a gate and a drain thereof being supplied with a power supply voltage, a resistor connected between a source of the NMOS transistor and a ground potential, and a source voltage detection circuit receiving a voltage of the source, wherein an NMOS type transistor is employed as the NMOS transistor, a channel width and a channel length of the NMOS type transistor being set in such a manner that an operating point on a VG-ID curve of the NMOS type transistor may come to a certain point, at the certain point, a drain current of the NMOS type transistor being constant even if the temperature fluctuates.

摘要翻译： 本发明的电压检测电路包括NMOS晶体管二极管连接，其栅极和漏极被提供有电源电压，连接在NMOS晶体管的源极和接地电位之间的电阻和源电压检测 接收源的电压的电路，其中使用NMOS型晶体管作为NMOS晶体管，NMOS晶体管的沟道宽度和沟道长度被设置为使得在所述NMOS晶体管的VG-ID曲线上的工作点 NMOS型晶体管可以到达某一点，在某一点，即使温度波动，NMOS型晶体管的漏极电流恒定。

公开(公告)号：US07679412B2

公开(公告)日：2010-03-16

申请号：US12239188

申请日：2008-09-26

申请人： Ryu Ogiwara ,  Daisaburo Takashima

发明人： Ryu Ogiwara ,  Daisaburo Takashima

IPC分类号： H03L7/00

CPC分类号： G11C5/143 ,  G11C5/147

摘要： According to an aspect of the present invention, there is provided a power supply circuit including: a detection circuit that is connected to an external power supply voltage and that outputs a first signal indicating whether the external power supply voltage is in a dropped-state in which the external power supply voltage is dropped below a reference voltage; a control circuit that includes: a delay circuit that outputs a second signal acquired by delaying the first signal for a reference time; and a determination circuit that outputs a third signal based on the first signal and the second signal; a generation circuit that generates internal power supply voltage from the external power supply voltage and that supplies the internal power supply voltage; and an interruption circuit that interrupts the internal power supply voltage supplied from the generation circuit based on the third signal.

摘要翻译： 根据本发明的一个方面，提供一种电源电路，包括：检测电路，其连接到外部电源电压，并且输出指示外部电源电压是否处于丢弃状态的第一信号 外部电源电压降低到参考电压以下; 控制电路，包括：延迟电路，其输出通过将所述第一信号延迟参考时间获取的第二信号; 以及确定电路，其基于所述第一信号和所述第二信号输出第三信号; 生成电路，其从所述外部电源电压产生内部电源电压，并且提供所述内部电源电压; 以及中断电路，其基于所述第三信号中断从所述发电电路提供的内部电源电压。

公开(公告)号：US07589513B2

公开(公告)日：2009-09-15

申请号：US11783039

申请日：2007-04-05

申请人： Ryu Ogiwara ,  Daisaburo Takashima

发明人： Ryu Ogiwara ,  Daisaburo Takashima

IPC分类号： G05F3/16

CPC分类号： G05F3/30 ,  G11C5/147 ,  G11C7/04

摘要： A reference voltage generator circuit comprises a first current path and a second current path. The first current path is formed between an input terminal supplied with a first reference voltage and an output terminal and including a first diode and a first resistor serially connected from the input terminal. The second current path is formed between the input terminal and the output terminal and including a second diode, a second resistor and a third resistor serially connected from the input terminal. A comparator is supplied with a voltage on a node between the first diode and the first resistor and a voltage on a node between the second resistor and the third resistor for comparative amplification. A transistor is connected between the output terminal and a second reference voltage and having a control terminal to receive an output from the first comparator.

摘要翻译： 参考电压发生器电路包括第一电流路径和第二电流路径。 第一电流路径形成在提供有第一参考电压的输入端子和输出端子之间，并且包括第一二极管和从输入端子串联连接的第一电阻器。 第二电流路径形成在输入端子和输出端子之间，并且包括从输入端子串联连接的第二二极管，第二电阻器和第三电阻器。 比较器在第一二极管和第一电阻之间的节点上提供电压，并且在第二电阻器和第三电阻器之间的节点上的电压用于比较放大。 晶体管连接在输出端和第二参考电压之间，并且具有用于接收来自第一比较器的输出的控制端。

公开(公告)号：US07583114B2

公开(公告)日：2009-09-01

申请号：US11684214

申请日：2007-03-09

申请人： Ryu Ogiwara ,  Daisaburo Takashima

发明人： Ryu Ogiwara ,  Daisaburo Takashima

IPC分类号： H03L7/00

CPC分类号： G01R19/16552 ,  G01R19/16519 ,  G11C5/147

摘要： A supply voltage sensing circuit comprises an internal power supply circuit, which provides a constant output voltage regardless of the supply voltage. A delay circuit generates a delayed signal by delaying a variation in the output voltage. A divider circuit generates a divided voltage by dividing the supply voltage at a certain division ratio. A p-type MOS transistor has a source given the delayed signal and a gate given the divided voltage and turns on when the supply voltage lowers below a certain value. An output circuit provides an output voltage based on a drain voltage on the p-type MOS transistor.

摘要翻译： 电源电压检测电路包括内部电源电路，其提供恒定的输出电压，而不管电源电压如何。 延迟电路通过延迟输出电压的变化来产生延迟信号。 分压电路通过以一定的分频比除电源电压来产生分压。 p型MOS晶体管具有给定延迟信号的源极和给定分压的栅极，并且当电源电压降低到一定值以下时导通。 输出电路基于p型MOS晶体管上的漏极电压提供输出电压。

公开(公告)号：US20090115387A1

公开(公告)日：2009-05-07

申请号：US12266143

申请日：2008-11-06

申请人： Ryu OGIWARA ,  Daisaburo TAKASHIMA

发明人： Ryu OGIWARA ,  Daisaburo TAKASHIMA

IPC分类号： G05F1/10

CPC分类号： G05F1/575 ,  G05F3/16 ,  Y10T307/50

摘要： A voltage generating circuit comprising: a switching device which includes a first end connected to a high potential side power source, and which becomes conductive in a first mode and becomes non-conductive in a second mode; a first transistor including a first main electrode connected to a second end of the switching device, a second main electrode connected to an output terminal, and a gate connected to a gate potential supply node; a second transistor including a first main electrode connected to the high potential side power source, a second main electrode connected to the output terminal, and a gate connected to the gate potential supply node; and a gate voltage stabilizing circuit that suppresses a fluctuation in potential of the potential supply node, the fluctuation accompanying a change between the first and second modes.

摘要翻译： 一种电压产生电路，包括：开关装置，其包括连接到高电位侧电源的第一端，并且在第一模式中变为导通并且在第二模式中变为不导通; 第一晶体管，包括连接到开关装置的第二端的第一主电极，连接到输出端子的第二主电极和连接到栅极电位供应节点的栅极; 第二晶体管，包括连接到高电位侧电源的第一主电极，连接到输出端子的第二主电极和连接到栅极电位供应节点的栅极; 以及抑制电源供给节点的电位波动的栅极电压稳定电路，伴随着第一和第二模式之间的变化的波动。