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71.发明授权公开(公告)号：US10484217B2
公开(公告)日：2019-11-19
申请号：US15606979
申请日：2017-05-26
Inventor： Eusebio Dicola , Elena Salurso , Jan Milsimer
IPC: H04L27/144 , H04L27/156 , H04L27/10 , G01R29/027 , H04L1/20 , H04L1/18 , H04L25/06
Abstract: An occurrence of a first set of n periods of a frequency-shift-keying (FSK)-modulated waveform is counted, where n is an integer number. The n periods of the FSK-modulated waveform in the first set have a first time duration. An occurrence of a second set of n periods of the waveform is counted. The n periods of the waveform in the second set have a second time duration. The first time duration is determined based on the counting of the first set of n periods. The second time duration is determined based on the counting of the second set of n periods. A difference between the first time duration and the second time duration is compared to a threshold. Changes in frequency of the waveform are detected based on the comparing of the difference between the first time duration and the second time duration to the threshold.
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公开(公告)号：US20190334366A1
公开(公告)日：2019-10-31
申请号：US15964793
申请日：2018-04-27
Inventor： Karel BLAHA , Martin DRINOVSKY
Abstract: An analog ping signal that is present at a secondary coil of a power receiving device operating within a wireless power transmission system is detected. The detection circuit includes a DC blocking circuit having an input directly connected to a terminal of the secondary coil. A comparator circuit has an input coupled to an output of the DC blocking circuit. A timer circuit is reset by a signal output by the comparator circuit to assert a ping detect signal in response to a resetting of the timer circuit. The ping detect signal is deasserted in response to a timing out of the timer circuit.
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公开(公告)号：US10147796B1
公开(公告)日：2018-12-04
申请号：US15606778
申请日：2017-05-26
Inventor： Patrik Vacula , Milos Vacula , Vlastimil Kote , Adam Kubacak , Milan Lzicar
IPC: H01L29/423 , H01L27/088 , H01L29/06 , H01L29/40 , H01L29/66 , H01L29/778
Abstract: The present disclosure is directed to a plurality of waffle gate parallel transistors having a shared gate on a surface of a semiconductor substrate. The shared gate has connected channels that form a plurality of squares, lines of each of the squares over the perimeter of a respective source or drain region of the plurality of waffle gate parallel transistors. The shared gate includes squares of a first size and shape and a second size and shape. The squares having the first size and shape are each over a respective source region and the squares having the second size and shape are each over a respective drain region. Each of the squares having a first size and shape share at least one side with one of the squares having the second size and shape.
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公开(公告)号：US20180342504A1
公开(公告)日：2018-11-29
申请号：US15606773
申请日：2017-05-26
Inventor： Patrik Vacula , Milos Vacula , Miroslav Husak
IPC: H01L27/085 , H01L29/778 , H01L29/66 , H01L29/10 , H01L29/423
CPC classification number: H01L27/085 , H01L29/1033 , H01L29/2003 , H01L29/41766 , H01L29/42316 , H01L29/4232 , H01L29/66431 , H01L29/66462 , H01L29/7786 , H01L29/7788 , H01L29/78
Abstract: The present disclosure is directed to a plurality of waffle gate parallel transistors having a shared gate on a surface of a semiconductor substrate. The shared gate has connected lines that form a plurality of frames, lines of each of the frames being over the perimeter of a respective source or drain region. The shared gate includes frames of a first size and shape and frames of a second size and shape, such as squares, rectangles and octagons. The frames having the first size and shape are each over a respective source region and the frames having the second size and shape are each over a respective drain region. Each of the frames having a first size and shape share at least one side with one of the frames having the second size and shape.
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公开(公告)号：US20180120876A1
公开(公告)日：2018-05-03
申请号：US15336029
申请日：2016-10-27
Inventor： Sandor PETENYI
CPC classification number: G05F1/575 , H03F3/45071 , H03F3/45183 , H03F3/45475 , H03F2203/45116 , H03F2203/45154 , H03F2203/45274
Abstract: A voltage regulator having bias current boosting is provided. The voltage regulator includes a power stage for providing an output voltage to a load. The voltage regulator includes a differential stage that receives a feedback voltage representative of the output voltage and a reference voltage and controls the power stage based on a difference between the reference voltage and the feedback voltage. The voltage regulator includes a bias current boosting stage that receives the feedback and reference voltages. The bias current boosting stage provides a boosted bias current having a current level that is based on the difference between the reference and feedback voltages. The boosted bias current biases the differential stage and hastens a response of the differential stage, in response to a change in the difference between the reference voltage and the feedback voltage, in controlling the power stage.
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Patent Agency Ranking
公开(公告)号：US09864395B1
公开(公告)日：2018-01-09
申请号：US15367628
申请日：2016-12-02
Applicant: STMicroelectronics Design and Application S.R.O , STMicroelectronics Asia Pacific Pte Ltd
Inventor： Roman Prochazka , Chee Weng Cheong
IPC: G05F3/26
CPC classification number: G05F3/267
Abstract: A current mirror circuit includes an input current leg and an output current leg. The input current leg includes: a first bipolar junction transistor (BJT) having a collector terminal configured to receive an input current sourced at a current node and a first metal oxide semiconductor field effect transistor (MOSFET) having a gate terminal coupled to the current node and a source terminal coupled to a base terminal of the first BJT. The output current leg includes: a second BJT having a collector terminal configured to supply an output current and a second MOSFET having a gate terminal coupled to the current node and a source terminal coupled to a base terminal of the second BJT.
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公开(公告)号：US20160020627A1
公开(公告)日：2016-01-21
申请号：US14869253
申请日：2015-09-29
Inventor： Christophe Lorin , Benedicte Micheau , Roman Prochazka , Vaclav Jelen , Ondrej Plachy
CPC classification number: H02J7/0054 , G06F1/266 , G06F1/3203 , G06F1/3215 , G06F1/3234 , G06F1/3246 , G06F1/3287 , H02J7/0047 , H02J7/007 , H02J7/345 , H02J2007/0049 , H02J2007/0062
Abstract: A method of charging a battery of a device using a battery of a computer powered by the battery, in which the procedure is implemented by a circuit independent of the computer's processors. The method includes supplying a power supply voltage, insufficient to charge a battery, to a computer port, as long as a device is detected as connected to the port, controlling the supply of a charging voltage to the port, while supplying charging voltage to the port, detecting an end of charging condition of a battery of the device, and controlling the cutting off of the charging voltage to the port if the end of charging condition is detected, where this condition is determined according to the intensity of a charging current and according to a quantity of electrical charge supplied to the port and/or of a charging period.
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78.发明授权公开(公告)号：US09176567B2
公开(公告)日：2015-11-03
申请号：US13904866
申请日：2013-05-29
Inventor： Christophe Lorin , Benedicte Micheau , Roman Prochazka , Vaclav Jelen , Ondrej Plachy
CPC classification number: H02J7/0054 , G06F1/266 , G06F1/3203 , G06F1/3215 , G06F1/3234 , G06F1/3246 , G06F1/3287 , H02J7/0047 , H02J7/007 , H02J7/345 , H02J2007/0049 , H02J2007/0062
Abstract: A method of charging a battery of a device using a battery of a computer powered by the battery, in which the procedure is implemented by a circuit independent of the computer's processors. The method includes supplying a power supply voltage, insufficient to charge a battery, to a computer port, as long as a device is detected as connected to the port, controlling the supply of a charging voltage to the port, while supplying charging voltage to the port, detecting an end of charging condition of a battery of the device, and controlling the cutting off of the charging voltage to the port if the end of charging condition is detected, where this condition is determined according to the intensity of a charging current and according to a quantity of electrical charge supplied to the port and/or of a charging period.
Abstract translation: 一种使用由电池供电的计算机的电池对装置的电池进行充电的方法，其中该过程由独立于计算机的处理器的电路实现。 该方法包括向计算机端口提供不足以对电池充电的电源电压，只要检测到设备连接到端口，控制向端口提供充电电压，同时向该端口提供充电电压 端口，检测设备的电池的充电状态的结束，并且如果检测到充电状态的结束，则控制对端口的充电电压的切断，其中该条件根据充电电流的强度确定，并且 根据提供给端口的电量和/或充电期间。
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公开(公告)号：US09035639B2
公开(公告)日：2015-05-19
申请号：US13711454
申请日：2012-12-11
Inventor： Martin Drinovsky
CPC classification number: G05F1/46 , G05F1/561 , H02M3/156 , H02M2001/0009
Abstract: The present disclosure is directed to a voltage-to-current sensing circuit having a bias terminal configured to receive a reference voltage, an offset terminal configured to receive an offset current, and an operational amplifier configured to output a low voltage signal. The device includes a first amplifier having first and second high voltage inputs configured to receive a first voltage difference across a sense component on a high voltage line and to generate a first current, a second amplifier having first and second low voltage inputs configured to receive a second voltage difference between the bias terminal and the offset terminal and to generate a second current, a summing circuit configured to provide an intermediate voltage corresponding to a sum of the first and the second currents, and a low-voltage transistor coupled to an output of the amplifier and controlled by the intermediate voltage to generate the output current.
Abstract translation: 本公开涉及具有被配置为接收参考电压的偏置端子的电压到电流感测电路，被配置为接收偏移电流的偏移端子和被配置为输出低电压信号的运算放大器。 该器件包括具有第一和第二高电压输入的第一放大器，该第一和第二高电压输入被配置为接收高电压线上的感测元件上的第一电压差并产生第一电流，第二放大器具有第一和第二低电压输入， 偏置端子和偏移端子之间的第二电压差并产生第二电流，求和电路被配置为提供对应于第一和第二电流的和的中间电压，以及耦合到第一和第二电流的输出的低压晶体管 该放大器由中间电压控制，以产生输出电流。
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公开(公告)号：US20130154595A1
公开(公告)日：2013-06-20
申请号：US13711454
申请日：2012-12-11
Inventor： Martin Drinovsky
IPC: G05F1/46
CPC classification number: G05F1/46 , G05F1/561 , H02M3/156 , H02M2001/0009
Abstract: The present disclosure is directed to a voltage-to-current sensing circuit having a bias terminal configured to receive a reference voltage, an offset terminal configured to receive an offset current, and an operational amplifier configured to output a low voltage signal. The device includes a first amplifier having first and second high voltage inputs configured to receive a first voltage difference across a sense component on a high voltage line and to generate a first current, a second amplifier having first and second low voltage inputs configured to receive a second voltage difference between the bias terminal and the offset terminal and to generate a second current, a summing circuit configured to provide an intermediate voltage corresponding to a sum of the first and the second currents, and a low-voltage transistor coupled to an output of the amplifier and controlled by the intermediate voltage to generate the output current.
Abstract translation: 本公开涉及具有被配置为接收参考电压的偏置端子的电压到电流感测电路，被配置为接收偏移电流的偏移端子和被配置为输出低电压信号的运算放大器。 该器件包括具有第一和第二高电压输入的第一放大器，该第一和第二高电压输入被配置为接收高电压线上的感测元件上的第一电压差并产生第一电流，第二放大器具有第一和第二低电压输入， 偏置端子和偏移端子之间的第二电压差并产生第二电流，求和电路被配置为提供对应于第一和第二电流的和的中间电压，以及耦合到第一和第二电流的输出的低压晶体管 该放大器由中间电压控制，以产生输出电流。
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