公开(公告)号：US20230280929A1

公开(公告)日：2023-09-07

申请号：US17679120

申请日：2022-02-24

Applicant: Silicon Motion, Inc.

Inventor： Tsu-Han Lu ,  Hsiao-Chang Yen

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/061 ,  G06F3/0679

Abstract: A flash memory scheme simplifies the command sequences transmitted between a flash memory device and a flash memory controller into a simplified command sequence so as to reduce the waiting time period of the command transmission and improve the performance of flash memory.

公开(公告)号：US11748023B2

公开(公告)日：2023-09-05

申请号：US17025004

申请日：2020-09-18

Applicant: Silicon Motion, Inc.

Inventor： Yu-Hsiang Chung

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: Power recovery for data storage devices with an efficient space trimming technology is shown. A controller scans a non-volatile memory according to a programming order, collects a sequence of trimming information flags, and interprets a sequence of storage information scanned from the non-volatile memory to identify logical addresses and trimming code. Based on the logical addresses, a host-to-device mapping (H2F) table is rebuilt. Based on the trimming code, information of medium-length trimming and information of long-length trimming are recognized from a storage area of the non-volatile memory. According to the trimming information for medium-length trimming, dummy mapping data is programmed to the H2F table. According to the trimming information for long-length trimming, a trimming bitmap (TBM) is rebuilt. Each bit in the TBM marks space trimming of a first length.

公开(公告)号：US11748022B2

公开(公告)日：2023-09-05

申请号：US17519685

申请日：2021-11-05

Applicant: Silicon Motion, Inc.

Inventor： Sheng-I Hsu

IPC: G06F3/06

CPC classification number: G06F3/0653 ,  G06F3/0604 ,  G06F3/068 ,  G06F3/0656 ,  G06F3/0679 ,  G06F3/0683

Abstract: The invention introduces an apparatus for controlling different types of storage units, at least including: an interface and a processing unit. The interface connects at least two types of storage units, which include at least a nonvolatile hybrid memory. The processing unit is configured to operably access data to the different types of storage units through the interface.

公开(公告)号：US11726686B2

公开(公告)日：2023-08-15

申请号：US17843691

申请日：2022-06-17

Applicant: SILICON MOTION INC.

Inventor： Chao-Kuei Hsieh

IPC: G06F3/06 ,  G06F13/42

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0679 ,  G06F13/4221 ,  G06F2213/0026

Abstract: The present invention provides a method performed by a secure digital (SD) card supporting both an SD mode and a peripheral component interconnect express (PCIe) mode for initializing the SD card. The method includes: (a) after receiving a first supply voltage through a first voltage supply pin from a host coupled to the SD card, entering the SD mode if the SD card is not in the PCIe mode and a CMD0 command for entering the SD mode is received through a command pin from the host coupled to the SD card; and (b) after receiving the first supply voltage through the first voltage supply pin from the host coupled to the SD card, performing a PCIe linkup process if the SD card is not in the SD mode and a second supply voltage is received through a second voltage supply pin from the host coupled to the SD card. The SD card enters the PCIe mode if the PCIe linkup process succeeds.

公开(公告)号：US11705907B2

公开(公告)日：2023-07-18

申请号：US17707992

申请日：2022-03-30

Applicant: Silicon Motion, Inc.

Inventor： Tien-Hsing Yao ,  Chun-Cheng Lee ,  Sheng-I Hsu

IPC: H03K21/02 ,  H03K21/08 ,  H03K21/10 ,  G06F1/3234 ,  H03K5/00 ,  H03K21/40

CPC classification number: H03K21/026 ,  G06F1/3275 ,  H03K5/00006 ,  H03K21/10 ,  H03K21/406

Abstract: The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.

公开(公告)号：US11704234B2

公开(公告)日：2023-07-18

申请号：US16860093

申请日：2020-04-28

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang

IPC: G06F12/02 ,  G11C16/28 ,  G11C16/08 ,  G11C16/04 ,  G06F3/06 ,  G06F9/4401

CPC classification number: G06F12/0246 ,  G06F3/064 ,  G06F3/0608 ,  G06F3/0634 ,  G06F3/0659 ,  G06F3/0679 ,  G06F9/4401 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/28 ,  G06F2212/7201

Abstract: The present invention provides a method for accessing a flash memory module is disclosed, wherein the flash memory module includes at least one flash memory chip, each flash memory chip includes a plurality of block, each block is implemented by a plurality of word lines, each word line corresponds to K pages, and each word line includes a plurality of memory cells supporting a plurality of states, and the method includes the steps of: receiving data from a host device; generating dummy data; and writing the data with the dummy data to a plurality of specific blocks, wherein for each of a portion of the word lines of the specific blocks, the dummy data is written into at least one of the K pages, and the data from the host device is written into the other page(s) of the K pages.

公开(公告)号：US20230198754A1

公开(公告)日：2023-06-22

申请号：US18076615

申请日：2022-12-07

Applicant: Silicon Motion, Inc.

Inventor： Wun-Jhe WU ,  Po-Hung CHEN ,  Chiao-Wen CHENG ,  Jiun-Hung YU ,  Chih-Wei LIU

IPC: H04L9/08 ,  H04L9/06

CPC classification number: H04L9/0891 ,  H04L9/0631 ,  H04L9/0861

Abstract: The invention introduces an apparatus for detecting errors during data encryption. The apparatus includes a key generation circuitry and a key-error detection circuitry. The key generation circuitry is arranged operably to realize a key expansion operation for generating multiple round keys based on a root key in an encryption algorithm, where the encryption algorithm encodes plaintext or an intermediate encryption result with one round key in a corresponding round. The error detection circuitry is arranged operably to: calculate redundant data corresponding to each round key; and output an error signal to a processing unit when finding that any round key does not match corresponding redundant data at a check point during the key expansion operation.

公开(公告)号：US11664056B2

公开(公告)日：2023-05-30

申请号：US17723989

申请日：2022-04-19

Applicant: Silicon Motion, Inc.

Inventor： Wen-Sheng Lin

IPC: G11C5/14

CPC classification number: G11C5/141 ,  G11C5/147

Abstract: The invention relates to a method, and an apparatus for accessing to data in response to a power-supply event. The method, performed by a flash controller, includes steps for: reading a plurality of physical pages of data in a current block from a flash module during a sudden power off recovery procedure; determining whether a power-supply event has occurred according to an error correction result corresponding to read physical pages; reconstructing a first flash-to-host mapping (F2H) table to include physical-to-logical mapping (P2L) information from the 0th page to a page before a last valid page in the current block when the power-supply event has occurred; and programming the reconstructed first F2H table into a location of the flash module.

公开(公告)号：US11656791B2

公开(公告)日：2023-05-23

申请号：US17329189

申请日：2021-05-25

Applicant: Silicon Motion, Inc.

Inventor： Shen-Ting Chiu

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0611 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0679

Abstract: A memory controller coupled to a memory device and a host device and configured to control access operations of the memory device includes a buffer memory, a host interface, a microprocessor and a data protection engine. The host interface is coupled to the host device and configured to write data received from the host device into the buffer memory and issue a buffer memory write complete notification after the data has been written in the buffer memory. The microprocessor is configured to trigger a data protection operation in response to the buffer memory write complete notification. The protection engine is configured to perform the data protection operation to generate corresponding protection information according to the data written in the buffer memory. The microprocessor is configured to directly trigger the data protection operation after confirming that the data has been written in the buffer memory.

公开(公告)号：US20230141572A1

公开(公告)日：2023-05-11

申请号：US18092908

申请日：2023-01-03

Applicant: Silicon Motion, Inc.

Inventor： Tien-Hsing Yao ,  Chun-Cheng Lee ,  Sheng-I Hsu

IPC: H03K21/02 ,  H03K21/10 ,  G06F1/3234 ,  H03K5/00 ,  H03K21/40

CPC classification number: H03K21/026 ,  H03K21/10 ,  G06F1/3275 ,  H03K5/00006 ,  H03K21/406

Abstract: The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.