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150 条记录 (耗时 0.073 秒)

    Plasma display panel and method of driving the same
    74.
    发明申请
    Plasma display panel and method of driving the same 审中-公开
    等离子显示面板及其驱动方法

    公开(公告)号：US20080252564A1

    公开(公告)日：2008-10-16

    申请号：US12081299

    申请日：2008-04-14

    申请人： In-Ju Choi ,  Woo-Joon Chung ,  Seong-Joon Jeong ,  Tae-Seong Kim

    发明人： In-Ju Choi ,  Woo-Joon Chung ,  Seong-Joon Jeong ,  Tae-Seong Kim

    IPC分类号： G09G3/28

    CPC分类号： G09G3/2927 ,  G09G3/2022 ,  G09G2310/066 ,  G09G2320/0238

    摘要： Provided is a method of driving a plasma display panel (PDP) that comprises X electrodes, Y electrodes, and address electrodes, wherein a frame, which is a display cycle, comprises a plurality of subfields for time-divisional gray scale display. Each of the subfields includes a reset period, an address period, and a sustain period. The reset period is one of a main reset period during which both a rising pulse and a falling pulse are applied to the Y electrodes and an auxiliary reset period during which one of the rising pulse and the falling pulse is applied to the Y electrodes, and the main reset period comprises a first pulse time during which a pulse rising to a level of a first voltage and then falling to a level of a second voltage is applied to the Y electrodes and a second pulse time during which a pulse rising to a level of a third voltage and then falling to a level of a fourth voltage is applied to the Y electrodes.

    摘要翻译： 提供了一种驱动包括X电极，Y电极和寻址电极的等离子体显示面板（PDP）的方法，其中作为显示周期的框架包括用于时分分割灰度显示的多个子场。 每个子场包括复位周期，地址周期和维持周期。 复位期间是向Y电极施加上升脉冲和下降脉冲的主复位期间和向Y电极施加上升脉冲和下降脉冲之一的辅助复位期间之一， 主复位周期包括第一脉冲时间，在该第一脉冲时间期间，将上升到第一电压的电平然后下降到第二电压的电平的脉冲施加到Y电极和第二脉冲时间，在该第二脉冲时间期间脉冲上升到电平 的第三电压，然后下降到第四电压的电平施加到Y电极。

    Plasma display and driving method thereof
    75.
    发明申请
    Plasma display and driving method thereof 审中-公开
    等离子体显示及其驱动方法

    公开(公告)号：US20080122753A1

    公开(公告)日：2008-05-29

    申请号：US11976328

    申请日：2007-10-23

    申请人： Tae-Seong Kim ,  Seung-Won Choi ,  Seong-Joon Jeong ,  Woo-Joon Chung

    发明人： Tae-Seong Kim ,  Seung-Won Choi ,  Seong-Joon Jeong ,  Woo-Joon Chung

    IPC分类号： G09G3/28

    CPC分类号： G09G3/2932 ,  G09G3/2942 ,  G09G2310/06 ,  G09G2320/0233

    摘要： In a plasma display device, an elapsed driving time of the plasma display device is accumulated and calculated, and a scan pulse having a first voltage is supplied to a scan electrode during a first period which is an address period of each subfield in response to the accumulated driving time being less than a reference time, and a scan pulse having a second voltage that is greater than the first voltage is supplied to a scan electrode during a second period which is an address period of each subfield in response to the accumulated driving time being greater than the reference time.

    摘要翻译： 在等离子体显示装置中，累积和计算等离子体显示装置的经过的驱动时间，并且在作为响应于每个子场的地址周期的第一周期期间，向扫描电极提供具有第一电压的扫描脉冲 累积的驱动时间小于参考时间，并且具有大于第一电压的第二电压的扫描脉冲在响应于累积的驱动时间的每个子场的寻址周期的第二周期期间被提供给扫描电极 大于参考时间。

    Plasma display panel driving method
    76.
    发明授权
    Plasma display panel driving method 失效
    等离子显示面板驱动方式

    公开(公告)号：US07355565B2

    公开(公告)日：2008-04-08

    申请号：US10974946

    申请日：2004-10-28

    申请人： Jin-Sung Kim ,  Woo-Joon Chung ,  Seung-Hun Chae ,  Kyoung-Ho Kang ,  Tae-Seong Kim

    发明人： Jin-Sung Kim ,  Woo-Joon Chung ,  Seung-Hun Chae ,  Kyoung-Ho Kang ,  Tae-Seong Kim

    IPC分类号： G09G3/28

    CPC分类号： G09G3/2942 ,  G09G2330/021 ,  G09G2360/16

    摘要： A method for driving a display panel including a first electrode, a second electrode and an address electrode crossed with the first and second electrodes to form a discharge cell. The method comprises, during a sustain period, alternately applying a voltage pulse to the first and second electrodes, and floating the first or the second electrode and maintaining it at a first voltage level while the voltage pulse is applied to the other electrode.

    摘要翻译： 一种用于驱动显示面板的方法，包括与第一和第二电极交叉的第一电极，第二电极和寻址电极，以形成放电单元。 该方法包括在维持周期期间，交替地向第一和第二电极施加电压脉冲，并且在将电压脉冲施加到另一个电极的同时使第一或第二电极浮置并将其保持在第一电压电平。

    Flash memory devices with flash fuse cell arrays
    80.
    发明申请
    Flash memory devices with flash fuse cell arrays 有权

    公开(公告)号：US20060176740A1

    公开(公告)日：2006-08-10

    申请号：US11346520

    申请日：2006-02-02

    申请人： Tae-Seong Kim ,  Gyu-Hong Kim

    发明人： Tae-Seong Kim ,  Gyu-Hong Kim

    IPC分类号： G11C16/04

    CPC分类号： G11C29/021 ,  G11C16/04 ,  G11C16/0425 ,  G11C29/028 ,  G11C29/789 ,  G11C29/82

    摘要： A flash memory device includes a flash cell array, a first flash fuse cell fusing circuit, a second flash fuse cell fusing circuit, a third flash fuse cell fusing circuit and a plurality of fuse sense amplifying circuits. The first, second and third flash fuse cell fusing circuits all share bit lines with a flash cell array and have flash fuse cells. The first flash fuse cell fusing circuit may be used to control a connection between the flash cell array and an external logic circuit. The second flash fuse cell fusing circuit may be used to change an address of a defective cell into an address of a redundancy cell. The third flash fuse cell fusing circuit may be used to control a DC level for adjusting a reference value used in a manufacturing process of the flash memory device. The fuse sense amplifying circuits are coupled to the bit lines to read data from the bit lines, respectively.