公开(公告)号：US09026975B2

公开(公告)日：2015-05-05

申请号：US13800483

申请日：2013-03-13

申请人： Tae-joong Song ,  Pil-un Ko ,  Gyu-hong Kim ,  Jong-hoon Jung

发明人： Tae-joong Song ,  Pil-un Ko ,  Gyu-hong Kim ,  Jong-hoon Jung

IPC分类号： G06F17/50 ,  H01L27/092 ,  H01L27/02

CPC分类号： G06F17/5072 ,  G06F17/50 ,  G06F17/5077 ,  G06F17/5081 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/6681

摘要： A semiconductor integrated circuit designing method capable of minimizing a parasitic capacitance generated by an overhead in conductive lines, especially a gate line, a semiconductor integrated circuit according to the designing method, and a fabricating method thereof are provided. A method of designing a semiconductor integrated circuit having a FinFET architecture, includes: performing a pre-simulation of the semiconductor integrated circuit to be designed; designing a layout of components of the semiconductor integrated circuit based on a result of the pre-simulation, the components comprising first and second device areas and a first conductive line extending across the first and second device areas; modifying a first cutting area, that is arranged between the first and second device areas and electrically cuts the first conductive line, according to at least one design rule to minimize an overhead of the first conductive line created by the first cutting area.

摘要翻译： 提供了一种半导体集成电路设计方法及其制造方法，该方法能够最小化由导线，特别是栅极线，半导体集成电路中的开销产生的寄生电容及其制造方法。 一种设计具有FinFET架构的半导体集成电路的方法，包括：对要设计的半导体集成电路进行预仿真; 基于预仿真的结果设计半导体集成电路的部件的布局，所述部件包括第一和第二器件区域以及跨越第一和第二器件区域延伸的第一导电线; 根据至少一个设计规则修改布置在第一和第二设备区域之间并且电切割第一导电线的第一切割区域，以使由第一切割区域产生的第一导电线路的开销最小化。

公开(公告)号：US06927999B2

公开(公告)日：2005-08-09

申请号：US10719265

申请日：2003-11-21

申请人： Soung-Hoon Sim ,  Hyo-Sang Lee ,  Gyu-Hong Kim

发明人： Soung-Hoon Sim ,  Hyo-Sang Lee ,  Gyu-Hong Kim

IPC分类号： G11C16/06 ,  G11C11/34 ,  G11C16/02 ,  G11C16/04 ,  G11C16/10 ,  G11C16/30 ,  H01L27/115

CPC分类号： G11C16/0425 ,  G11C16/10 ,  G11C16/30

摘要： An integrated circuit memory device includes a source line and a memory cell array that includes n memory cells that are connected to the source line. The n memory cells are operative to draw current from the source line in response to an n bit data word. A dummy memory cell circuit is operative to draw current from the source line responsive to the n bit data word such that a total current drawn by the memory cell array and the dummy memory cell circuit during a program operation is given by n*a current drawn by one of the n memory cells.

摘要翻译： 集成电路存储器件包括源极线和包括连接到源极线的n个存储器单元的存储单元阵列。 n个存储器单元可操作以响应于n位数据字从源极线引出电流。 虚拟存储单元电路用于响应于n位数据字从源极线抽取电流，使得在编程操作期间由存储器单元阵列和虚拟存储器单元电路绘制的总电流由n * a给出 通过n个存储单元之一。

公开(公告)号：US20050057976A1

公开(公告)日：2005-03-17

申请号：US10874604

申请日：2004-06-23

申请人： Jong-doo Joo ,  Gyu-hong Kim

发明人： Jong-doo Joo ,  Gyu-hong Kim

IPC分类号： G11C7/10 ,  H02G3/00

CPC分类号： G11C7/1012 ,  G11C7/1006 ,  G11C2207/104 ,  G11C2207/2227

摘要： Provided are a low power consumption data input/output circuit of an embedded memory device and a data input/output method of the circuit. The embedded memory device includes sub memory cell blocks that share word lines. The data input/output circuit includes input/output lines, bit line sense amplifying unit groups, and data input/output units. Each pair of the input/output lines is arranged in each of the sub memory cell blocks. The bit line sense amplifying unit groups are connected between the sub memory cell blocks and the pairs of input/output lines and mutually transmit data signals between the sub memory cell blocks and the pairs of input/output lines in response to first control signals. Each of the data input/output units is connected to each of input/output line groups each including a first predetermined number of pairs of the input/output lines, selects as a data output path some of the input/output lines included in each of the input/output line groups in response to second control signals, pre-discharges the residual input/output lines to a ground voltage, and receives and transmits the data signals to the sub memory cell blocks via the selected input/output lines.

摘要翻译： 提供了嵌入式存储器件的低功耗数据输入/输出电路和电路的数据输入/输出方法。 嵌入式存储器件包括共享字线的子存储器单元块。 数据输入/输出电路包括输入/​​输出线，位线检测放大单元组和数据输入/输出单元。 每对输入/输出线被布置在每个子存储单元块中。 位线读出放大单元组连接在子存储单元块和输入/输出对之间，并且响应于第一控制信号在子存储单元块和输入/输出对之间相互发送数据信号。 每个数据输入/输出单元连接到每个输入/输出线组，每组输入/输出线组包括第一预定数量的输入/输出线对，选择包括在每个输入/输出线中的一些输入/输出线作为数据输出路径 响应于第二控制信号的输入/输出线路组，将剩余输入/输出线预放电到接地电压，并且经由所选择的输入/输出线接收数据信号并发送到子存储器单元块。

公开(公告)号：USRE36532E

公开(公告)日：2000-01-25

申请号：US151414

申请日：1998-09-10

申请人： Gyu-Hong Kim

发明人： Gyu-Hong Kim

IPC分类号： G11C7/10 ,  G11C7/12 ,  G11C8/00

CPC分类号： G11C7/1072 ,  G11C7/12

摘要： A semiconductor memory device according to the present invention having a plurality of memory banks, a row address strobe signal buffer, a column address strobe signal buffer and a column address generator and performing a data access operation in response to the burst length and latency information related to a system clock having a predetermined frequency, comprises a device for generating a signal which automatically precharges one memory bank of the memory banks in response to the row address strobe signal and the signal having the burst length and latency information after an address operation for the memory bank is completed.

摘要翻译： 根据本发明的半导体存储器件具有多个存储体，行地址选通信号缓冲器，列地址选通信号缓冲器和列地址生成器，并且响应于突发长度和等待时间信息而执行数据存取操作 具有预定频率的系统时钟，包括用于响应于行地址选通信号和具有突发长度和等待时间信息的信号在一个地址操作之后产生一个信号的装置，该信号自动对存储体的一个存储体进行预充电 记忆库完成。

公开(公告)号：US5999463A

公开(公告)日：1999-12-07

申请号：US56426

申请日：1998-04-07

申请人： Youn-sik Park ,  Gyu-hong Kim

发明人： Youn-sik Park ,  Gyu-hong Kim

IPC分类号： H01L27/10 ,  G06F11/00 ,  G11C11/34 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/812 ,  G06F11/00 ,  G11C29/781

摘要： A semiconductor device having a reduced number of column redundancy fuse boxes include a plurality of memory blocks having normal and redundant memory cells, a plurality of normal column selection line drivers, a plurality of redundant column selection line drivers, and a column redundancy fuse box. In particular, the normal and redundant column selection line drivers all include fuses. The column redundancy fuse box is connected in common to the plurality of redundant column selection line drivers. Also, the redundancy fuse box comprises a repair address determining portion for pre-latching a repair address and comparing input addresses with the latched repair address to determine whether the input address is the same as the repair address, and a redundancy enable signal generating portion for generating a redundancy enable signal in response to the output signals of the repair address determining portion.

摘要翻译： 具有减少数量的列冗余熔丝盒的半导体器件包括具有正常和冗余存储单元的多个存储块，多个正常列选择线驱动器，多个冗余列选择线驱动器和列冗余保险丝盒。 特别地，正常和冗余的列选择线驱动器都包括保险丝。 列冗余保险丝盒共同连接到多个冗余列选择线驱动器。 此外，冗余保险丝盒包括修复地址确定部分，用于预先锁定修复地址，并将输入地址与锁存的修复地址进行比较，以确定输入地址是否与修复地址相同;以及冗余使能信号产生部分，用于 响应于修复地址确定部分的输出信号产生冗余使能信号。

公开(公告)号：US5555526A

公开(公告)日：1996-09-10

申请号：US397689

申请日：1995-03-02

申请人： Gyu-Hong Kim

发明人： Gyu-Hong Kim

IPC分类号： G11C11/409 ,  G11C7/12 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C11/407 ,  G11C8/00

CPC分类号： G11C7/12 ,  G11C8/12

摘要： A semiconductor memory device according to the present invention having a plurality of memory banks, a row address strobe signal buffer, a column address strobe signal buffer and a column address generator and performing a data access operation in response to the burst length and latency information related to a system clock having a predetermined frequency, comprises a device for generating a signal which automatically precharges one memory bank of the memory banks in response to the row address strobe signal and the signal having the burst length and latency information after an address operation for the memory bank is completed.

公开(公告)号：US08811069B2

公开(公告)日：2014-08-19

申请号：US13591696

申请日：2012-08-22

申请人： Gyu Hong Kim ,  Jong Hoon Jung

发明人： Gyu Hong Kim ,  Jong Hoon Jung

IPC分类号： G11C11/00

CPC分类号： G11C7/22 ,  G11C7/08 ,  G11C11/41 ,  G11C11/419 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012

摘要： The memory device includes a memory cell array, an access control circuit configured to access the memory cell array, a control signal generation circuit configured to generate a control signal for controlling an operation of the access control circuit, and a variable delay circuit configured to generate a delay signal by variably delaying a clock signal according to an external signal. The control signal generation circuit adjusts an activation timing of the control signal in response to the delay signal.

摘要翻译： 存储装置包括：存储单元阵列，被配置为存取存储单元阵列的访问控制电路;控制信号生成电路，被配置为产生用于控制访问控制电路的操作的控制信号;以及可变延迟电路， 通过根据外部信号可变延迟时钟信号的延迟信号。 控制信号发生电路根据延迟信号调整控制信号的激活定时。

公开(公告)号：US20130051129A1

公开(公告)日：2013-02-28

申请号：US13591696

申请日：2012-08-22

申请人： Gyu Hong KIM ,  Jong Hoon JUNG

发明人： Gyu Hong KIM ,  Jong Hoon JUNG

IPC分类号： G11C7/22 ,  G11C11/00

CPC分类号： G11C7/22 ,  G11C7/08 ,  G11C11/41 ,  G11C11/419 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012

摘要： The memory device includes a memory cell array, an access control circuit configured to access the memory cell array, a control signal generation circuit configured to generate a control signal for controlling an operation of the access control circuit, and a variable delay circuit configured to generate a delay signal by variably delaying a clock signal according to an external signal. The control signal generation circuit adjusts an activation timing of the control signal in response to the delay signal.

摘要翻译： 存储装置包括：存储单元阵列，被配置为存取存储单元阵列的访问控制电路;控制信号生成电路，被配置为产生用于控制访问控制电路的操作的控制信号;以及可变延迟电路， 通过根据外部信号可变延迟时钟信号的延迟信号。 控制信号发生电路根据延迟信号调整控制信号的激活定时。

公开(公告)号：US07852694B2

公开(公告)日：2010-12-14

申请号：US12155885

申请日：2008-06-11

申请人： Jong-hoon Jung ,  Gyu-hong Kim

发明人： Jong-hoon Jung ,  Gyu-hong Kim

IPC分类号： G11C7/00

CPC分类号： G11C7/12

摘要： A semiconductor memory device for reducing a precharge time is provided. The semiconductor memory device may include a sense amplifier, a precharge unit and an equalizing circuit. The sense amplifier may sense and amplify a difference between data transmitted through a first bit line and data transmitted through a second bit line in response to a sense amplifier enable signal. The precharge unit may precharge voltage levels of the first bit line and the second bit line to a precharge voltage level in response to a precharge enable signal. The equalizing circuit may be connected to the sense amplifier and the precharge unit and may control the voltage levels of the first bit line and the second bit line to be equal to each other in response to the sense amplifier enable signal. The semiconductor memory device may reduce a time required to perform a precharge operation and/or minimize an increase of the circuit size.

摘要翻译： 提供一种用于减少预充电时间的半导体存储器件。 半导体存储器件可以包括读出放大器，预充电单元和均衡电路。 感测放大器可以响应于读出放大器使能信号来感测和放大通过第一位线传输的数据与通过第二位线传输的数据之间的差异。 预充电单元可以响应于预充电使能信号而将第一位线和第二位线的电压电压预充电到预充电电压电平。 均衡电路可以连接到读出放大器和预充电单元，并且可以响应于读出放大器使能信号而将第一位线和第二位线的电压电平控制为彼此相等。 半导体存储器件可以减少执行预充电操作所需的时间和/或最小化电路尺寸的增加。

公开(公告)号：US07560974B2

公开(公告)日：2009-07-14

申请号：US11506035

申请日：2006-08-17

申请人： Kyong-Jun Noh ,  Gyu-Hong Kim

发明人： Kyong-Jun Noh ,  Gyu-Hong Kim

IPC分类号： H03K5/153 ,  H03K3/01 ,  H01L35/00 ,  G05F1/10

CPC分类号： G11C5/147 ,  G11C7/04 ,  G11C11/4074

摘要： A level detector within a back-bias voltage generator includes a toggling unit and a temperature detector. The toggling unit causes an enable signal to be activated when an absolute value of a back-bias voltage is less than an absolute value of a monitoring level. The temperature detector controls the toggling unit for increasing the absolute value of the monitoring level with an increase in temperature with high temperature sensitivity.

摘要翻译： 反向偏置电压发生器内的电平检测器包括切换单元和温度检测器。 当反偏置电压的绝对值小于监视电平的绝对值时，切换单元导致使能信号被激活。 温度检测器控制切换单元，以增加温度敏感度的温度升高来提高监控级别的绝对值。