公开(公告)号：US11194382B2

公开(公告)日：2021-12-07

申请号：US16162215

申请日：2018-10-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Kedarnath Balakrishnan

IPC: G06F1/32 ,  G06F1/3287 ,  G06F1/324 ,  G06F1/3296 ,  G11C7/22 ,  G06F1/3234 ,  G06F13/16 ,  G06F1/3228 ,  G06F1/3225 ,  G06F11/34

Abstract: A processing system includes a memory controller that preemptively exits a dynamic random access (DRAM) integrated circuit rank from a low power mode such as power down mode based on a predicted time when the memory controller will receive a request to access the DRAM rank. The memory controller tracks how long after a DRAM rank enters the low power mode before a request to access the DRAM rank is received by the memory controller. Based on a history of the timing of access requests, the memory controller predicts for each DRAM rank a predicted time reflecting how long after entering low power mode a request to access each DRAM rank is expected to be received. The memory controller speculatively exits the DRAM rank from the low power mode based on the predicted time and prior to receiving a request to access the DRAM IC rank.

公开(公告)号：US20210200618A1

公开(公告)日：2021-07-01

申请号：US16730113

申请日：2019-12-30

Applicant: Advanced Micro Devices, Inc.

Inventor： James R. Magro ,  Kedarnath Balakrishnan ,  Vilas Sridharan

IPC: G06F11/07 ,  G06F11/16 ,  G06F11/30 ,  G06F3/06

Abstract: A memory controller includes a command queue, a memory interface queue, and a non-volatile error reporting circuit. The command queue receives memory access commands including volatile reads, volatile writes, non-volatile reads, and non-volatile writes, and an output. The memory interface queue has an input coupled to the output of the command queue, and an output for coupling to a non-volatile storage class memory (SCM) module. The non-volatile error reporting circuit identifies error conditions associated with the non-volatile SCM module and maps the error conditions from a first number of possible error conditions associated with the non-volatile SCM module to a second, smaller number of virtual error types for reporting to an error monitoring module of a host operating system, the mapping based at least on a classification that the error condition will or will not have a deleterious effect on an executable process running on the host operating system.

公开(公告)号：US20210073152A1

公开(公告)日：2021-03-11

申请号：US17100254

申请日：2020-11-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Guanhao Shen ,  Ravindra N. Bhargava ,  Kedarnath Balakrishnan

IPC: G06F13/30 ,  G06F13/16 ,  G06F3/06

Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. When a memory controller in a computing system determines a threshold number of memory access requests have not been sent to the memory device in a current mode of a read mode and a write mode, a first cost corresponding to a latency associated with sending remaining requests in either the read queue or the write queue associated with the current mode is determined. If the first cost exceeds the cost of a data bus turnaround, the cost of a data bus turnaround comprising a latency incurred when switching a transmission direction of the data bus from one direction to an opposite direction, then a second cost is determined for sending remaining memory access requests to the memory device. If the second cost does not exceed the cost of the data bus turnaround, then a time for the data bus turnaround is indicated and the current mode of the memory controller is changed.

公开(公告)号：US10403333B2

公开(公告)日：2019-09-03

申请号：US15211887

申请日：2016-07-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl ,  Thomas Hamilton ,  Hideki Kanayama ,  Kedarnath Balakrishnan ,  James R. Magro ,  Guanhao Shen ,  Mark Fowler

IPC: G11C7/10 ,  G06F12/1018 ,  G11C11/408

Abstract: A memory controller includes a host interface for receiving memory access requests including access addresses, a memory interface for providing memory accesses to a memory system, and an address decoder coupled to the host interface for programmably mapping the access addresses to selected ones of a plurality of regions. The address decoder is programmable to map the access addresses to a first region having a non-power-of-two size using a primary decoder and a secondary decoder each having power-of-two sizes, and providing a first region mapping signal in response. A command queue stores the memory access requests and region mapping signals. An arbiter picks the memory access requests from the command queue based on a plurality of criteria, which are evaluated based in part on the region mapping signals, and provides corresponding memory accesses to the memory interface in response.

公开(公告)号：US10402120B2

公开(公告)日：2019-09-03

申请号：US15272626

申请日：2016-09-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan

IPC: G06F3/06 ,  G06F13/16

Abstract: In one form, an apparatus includes a memory controller. The memory controller includes a command queue and an arbiter. The command queue receives and stores memory access requests. The arbiter picks the memory access requests from the command queue based on a plurality of criteria, and provides picked memory access requests to a memory channel. The arbiter includes a streak counter for counting a number of consecutive memory access requests of a first type that the arbiter picks from the command queue. When the streak counter reaches a threshold, the arbiter suspends picking requests of the first type and picks at least one memory access request of a second type. The arbiter provides the at least one memory access request of the second type to the memory channel.

公开(公告)号：US20180018133A1

公开(公告)日：2018-01-18

申请号：US15272626

申请日：2016-09-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0683 ,  G06F13/1673

Abstract: In one form, an apparatus includes a memory controller. The memory controller includes a command queue and an arbiter. The command queue receives and stores memory access requests. The arbiter picks the memory access requests from the command queue based on a plurality of criteria, and provides picked memory access requests to a memory channel. The arbiter includes a streak counter for counting a number of consecutive memory access requests of a first type that the arbiter picks from the command queue. When the streak counter reaches a threshold, the arbiter suspends picking requests of the first type and picks at least one memory access request of a second type. The arbiter provides the at least one memory access request of the second type to the memory channel.

公开(公告)号：US09576637B1

公开(公告)日：2017-02-21

申请号：US15164721

申请日：2016-05-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan

IPC: G11C7/00 ,  G11C11/00 ,  G11C11/406 ,  G06F3/06

CPC classification number: G11C11/40611 ,  G06F3/0611 ,  G06F3/0634 ,  G06F3/0679 ,  G11C11/40603 ,  G11C11/40615

Abstract: A data processing system includes a memory channel and a data processor coupled to the memory channel. The data processor is adapted to access at least one rank and has refresh logic. In response to an activation of the refresh logic, the data processor generates refresh cycles to a bank of the memory channel. The data processor selects one of a first state corresponding to a first auto-refresh command that causes the data processor to auto-refresh the bank, and a second state corresponding to a second auto-refresh command that causes the data processor to auto-refresh a selected subset of the bank. The data processor initiates a switch between the first state and the second state in response to the refresh logic detecting a first condition related to the bank, and between the second state and the first state in response to the refresh logic circuit detecting a second condition.

Abstract translation: 数据处理系统包括存储器通道和耦合到存储器通道的数据处理器。 数据处理器适于访问至少一个等级并具有刷新逻辑。 响应于刷新逻辑的激活，数据处理器向存储器通道的存储体生成刷新周期。 数据处理器选择与导致数据处理器自动刷新存储体的第一自动刷新命令相对应的第一状态中的一个状态，以及与引起数据处理器自动刷新的第二自动刷新命令相对应的第二状态 银行的选定子集。 数据处理器响应于刷新逻辑检测与存储体相关的第一条件以及在第二状态和第一状态之间响应于刷新逻辑电路检测到第二条件而启动在第一状态和第二状态之间的切换。