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    Transistor switch having constant on resistance with input signal with having variable voltage component
    72.
    发明授权
    Transistor switch having constant on resistance with input signal with having variable voltage component 有权
    晶体管开关具有导通电阻，输入信号具有可变电压分量

    公开(公告)号：US09553578B2

    公开(公告)日：2017-01-24

    申请号：US14502899

    申请日：2014-09-30

    Applicant: APPLE INC.

    Inventor： Ahmad Al-Dahle ,  Hyunwoo Nho ,  Marduke Yousefpor ,  Weijun Yao ,  Yingxuan Li

    IPC: G05F1/10 ,  H03K17/687 ,  G09G3/36 ,  G09G3/20 ,  H03K17/14

    CPC classification number: H03K17/6872 ,  G09G3/20 ,  G09G3/3696 ,  G09G2300/08 ,  H03K17/145 ,  H03K17/687 ,  H03K2217/0054

    Abstract: Systems, methods, and devices to control a transistor to maintain one or more substantially constant characteristics while activated or deactivated are provided. One such system includes a transistor that receives an activation signal on a gate terminal to become activated during a first period and receives a deactivation signal on the gate terminal to become deactivated during a second period. The transistor receives an input signal on an input terminal during the first period and the second period. The input signal varies during the first period and during the second period. The transistor may have improved reliability (e.g., substantially constant on resistance RON) because a first difference between the input signal and the activation signal substantially does not vary during the first period and a second difference between the input signal and the deactivation signal substantially does not vary during the second period.

    Abstract translation: 提供了控制晶体管以在激活或去激活时维持一个或多个基本恒定特性的系统，方法和装置。 一个这样的系统包括晶体管，其在栅极端子处接收激活信号，以在第一时段期间被激活，并且在第二周期期间接收在栅极端子上的去激活信号以使其失效。 晶体管在第一周期和第二周期期间在输入端子上接收输入信号。 输入信号在第一周期和第二周期期间变化。 晶体管可能具有改进的可靠性（例如，基本上恒定的导通电阻RON），因为输入信号和激活信号之间的第一差异在第一周期内基本上不变，而输入信号和去激活信号之间的第二差基本上不是 在第二期间有所不同。

    DEVICES AND METHODS FOR REDUCING OR ELIMINATING MURA ARTIFACT ASSOCIATED WITH WHITE IMAGES
    73.
    发明申请
    DEVICES AND METHODS FOR REDUCING OR ELIMINATING MURA ARTIFACT ASSOCIATED WITH WHITE IMAGES 审中-公开
    用于减少或消除与白色图像相关的穆拉文化的设备和方法

    公开(公告)号：US20160071452A1

    公开(公告)日：2016-03-10

    申请号：US14794344

    申请日：2015-07-08

    Applicant: APPLE Inc.

    Inventor： Hyunwoo Nho ,  Hopil Bae ,  Wei H. Yao

    IPC: G09G3/20

    CPC classification number: G09G3/3674 ,  G09G3/3614 ,  G09G2310/0262 ,  G09G2320/0219 ,  G09G2320/0223 ,  G09G2320/0257

    Abstract: Devices and methods for reducing or eliminating image artifacts are provided. By way of example, a method of preventing an occurrence of an image artifact on a display panel may include generating a first gate signal to be supplied to a first gate of a first transistor, generating a second gate signal to be supplied to a second gate of a second transistor, and adjusting a falling edge rate of the first gate signal or a rising edge rate of the second gate signal to reduce a voltage drop associated with row pixels of the display panel. Adjusting the falling edge rate of the first gate signal or the rising edge rate of the second gate signal include decreasing the falling edge rate of the first gate signal or the rising edge rate of the second gate signal during a period of time in which the first gate signal falls.

    Abstract translation: 提供了用于减少或消除图像伪像的设备和方法。 作为示例，防止在显示面板上出现图像伪影的方法可以包括产生要提供给第一晶体管的第一栅极的第一栅极信号，产生要提供给第二栅极的第二栅极信号 并且调整第一栅极信号的下降沿速率或第二栅极信号的上升沿速率以减小与显示面板的行像素相关联的电压降。 调整第一栅极信号的下降沿率或第二栅极信号的上升沿速率包括在第一栅极信号的下降沿率或第二栅极信号的上升沿速率在第一栅极信号的第一 门信号下降。

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