公开(公告)号：US08234603B2

公开(公告)日：2012-07-31

申请号：US12835891

申请日：2010-07-14

申请人： Saeed Bagheri ,  David L. DeMaris ,  Maria Gabrani ,  David Osmond Melville ,  Alan E. Rosenbluth ,  Kehan Tian

发明人： Saeed Bagheri ,  David L. DeMaris ,  Maria Gabrani ,  David Osmond Melville ,  Alan E. Rosenbluth ,  Kehan Tian

IPC分类号： G06F17/50

CPC分类号： G03F1/70 ,  G06F17/5081

摘要： The present invention provides a lithographic difficulty metric that is a function of an energy ratio factor that includes a ratio of hard-to-print energy to easy-to-print energy of the diffraction orders along an angular coordinate θi of spatial frequency space, an energy entropy factor comprising energy entropy of said diffraction orders along said angular coordinate θi, a phase entropy factor comprising phase entropy of said diffraction orders along said angular coordinate θi, and a total energy entropy factor comprising total energy entropy of said diffraction orders. The hard-to-print energy includes energy of the diffraction orders at values of the normalized radial coordinates r of spatial frequency space in a neighborhood of r=0 and in a neighborhood of r=1, and the easy-to-print energy includes energy of the diffraction orders located at intermediate values of normalized radial coordinates r between the neighborhood of r=0 and the neighborhood of r=1. The value of the lithographic difficulty metric may be used to identify patterns in a design layout that are binding patterns in an optimization computation. The lithographic difficulty metric may be used to design integrated circuits that have good, relatively easy-to-print characteristics.

摘要翻译： 本发明提供了一种光刻难度度量，其是能量比因子的函数，能量比因子包括沿着角坐标和空间频率空间的角度i的衍射级的难以打印能量的容易打印能量的比率 包括沿着所述角坐标和所述角度坐标的所述衍射级的能量熵的能量熵因子; i，包括所述衍射级沿着所述角坐标系的所述衍射级的相位熵的相位熵因子; i，以及包括总能量熵的总能量熵因子 说衍射订单。 难以打印的能量包括在r = 0和r = 1附近的空间频率空间的归一化径向坐标r的值的衍射级的能量，并且易于打印的能量包括 位于r = 0的邻域和r = 1附近的归一化的径向坐标r的中间值处的衍射级的能量。 光刻难度度量的值可用于识别在优化计算中的结合模式的设计布局中的图案。 光刻难度度可用于设计具有良好，相对易于打印的特性的集成电路。

公开(公告)号：US20120047471A1

公开(公告)日：2012-02-23

申请号：US13204440

申请日：2011-08-05

申请人： Saeed Bagheri ,  Francisco Barahona ,  Laszlo Ladanyi ,  Jonathan Lee ,  David O. Melville ,  Alan E. Rosenbluth ,  Daniele P. Scarpazza ,  Marc A. Szeto-Millstone ,  Kehan Tian ,  Andreas Waechter

发明人： Saeed Bagheri ,  Francisco Barahona ,  Laszlo Ladanyi ,  Jonathan Lee ,  David O. Melville ,  Alan E. Rosenbluth ,  Daniele P. Scarpazza ,  Marc A. Szeto-Millstone ,  Kehan Tian ,  Andreas Waechter

IPC分类号： G06F17/50

CPC分类号： G03F1/36 ,  G03F1/68

摘要： A method for obtaining mask and source patterns for printing integrated circuit patterns includes providing initial representations of a plurality of mask and source patterns. The method identifies long-range and short-range factors in the representations of the plurality of mask and source patterns, and provides a plurality of clips including a specified number of mask patterns. Short-range factors having overlapping ranges for each of the clips are specified. The method includes determining an initial processing priority for the plurality of clips, and determining a patterning relationship between integrated circuit patterns and the mask and source patterns. A primary objective is determined which expresses the printability of the integrated circuit patterns in terms of the patterning relationship. The method defines and iteratively solves a master problem employing the primary objective to generate values for the long-range factors, and solves subproblems employing a second objective for generating values for the short-range factors.

摘要翻译： 用于获得用于打印集成电路图案的掩模和源图案的方法包括提供多个掩模和源图案的初始表示。 该方法识别多个掩模和源图案的表示中的长距离和短距离因子，并且提供包括指定数量的掩模图案的多个剪辑。 指定具有每个剪辑的重叠范围的短距离因子。 该方法包括确定多个剪辑的初始处理优先级，以及确定集成电路图案与掩模和源图案之间的图案化关系。 根据图案化关系确定表示集成电路图案的可印刷性的主要目的。 该方法定义并迭代地解决了使用主要目标生成长距离因子值的主问题，并且解决了使用第二个目标生成短距离因子值的子问题。

公开(公告)号：US08059885B2

公开(公告)日：2011-11-15

申请号：US12015768

申请日：2008-01-17

申请人： Jaione Tirapu-Azpiroz ,  Kafai Lai ,  David O. S. Melville ,  Alan E. Rosenbluth ,  Kehan Tian

发明人： Jaione Tirapu-Azpiroz ,  Kafai Lai ,  David O. S. Melville ,  Alan E. Rosenbluth ,  Kehan Tian

IPC分类号： G06K9/00

CPC分类号： G03F7/705 ,  G03F1/36

摘要： A method, system, computer program product and table lookup system for calculating image intensity for a mask used in integrated circuit processing are disclosed. A method may comprise: decomposing a Manhattan polygon of the mask into decomposed areas based on parallel edges of the Manhattan polygon along only one dimension; determining a convolution of each decomposed area based on a table lookup; determining a sum of coherent systems contribution of the Manhattan polygon based on the convolutions of the decomposed areas; and outputting the determined sum of coherent system contribution for analyzing the mask.

摘要翻译： 公开了一种用于计算集成电路处理中使用的掩模的图像强度的方法，系统，计算机程序产品和表查找系统。 方法可以包括：基于曼哈顿多边形沿着一个维度的平行边缘，将掩模的曼哈顿多边形分解为分解区域; 基于表查找确定每个分解区域的卷积; 基于分解区域的卷积确定曼哈顿多边形的相干系统贡献的总和; 并输出确定的用于分析掩模的相干系统贡献的总和。

公开(公告)号：US08056026B2

公开(公告)日：2011-11-08

申请号：US12334485

申请日：2008-12-14

申请人： Tadanobu Inoue ,  David O. Melville ,  Hidemasa Muta ,  Kehan Tian ,  Masahura Sakamoto ,  Alan E. Rosenbluth

发明人： Tadanobu Inoue ,  David O. Melville ,  Hidemasa Muta ,  Kehan Tian ,  Masahura Sakamoto ,  Alan E. Rosenbluth

IPC分类号： G06F17/50

CPC分类号： G03F1/68 ,  G03F1/78

摘要： The manufacturability of a lithographic mask employed in fabricating instances of a semiconductor device is determined. Target edges are selected from mask layout data of the lithographic mask. The mask layout data includes polygons distributed over cells, where each polygon has edges. The cells include a center cell, two vertical cells above and below the center cell, and two horizontal cells to the left and right of the center cell. Target edge pairs are selected for determining a manufacturing penalty in making the lithographic mask, in a manner that decreases the computational volume in determining the manufacturing penalty. The manufacturability of the lithographic mask, including the manufacturing penalty in making the lithographic mask, is determined based on the target edge pairs selected. The manufacturability of the lithographic mask is output. The manufacturability of the lithographic mask is dependent on the manufacturing penalty in making the lithographic mask.

摘要翻译： 确定用于制造半导体器件的实例的光刻掩模的可制造性。 从光刻掩模的掩模布局数据中选择目标边缘。 掩模布局数据包括分布在单元格上的多边形，其中每个多边形具有边。 小区包括中心小区，中心小区上方和下方的两个垂直小区以及中心小区左侧和右侧的两个水平小区。 选择目标边对以确定在制作光刻掩模时的制造损失，以减小计算体积来确定制造损失。 基于所选择的目标边缘对来确定光刻掩模的可制造性，包括制造光刻掩模的制造损失。 输出光刻掩模的可制造性。 光刻掩模的可制造性取决于制造光刻掩模的制造损失。

公开(公告)号：US08056023B2

公开(公告)日：2011-11-08

申请号：US12334482

申请日：2008-12-14

申请人： Tadanobu Inoue ,  David O. Melville ,  Hidemasa Muta ,  Kehan Tian ,  Masahura Sakamoto ,  Alan E. Rosenbluth

发明人： Tadanobu Inoue ,  David O. Melville ,  Hidemasa Muta ,  Kehan Tian ,  Masahura Sakamoto ,  Alan E. Rosenbluth

IPC分类号： G06F17/50

CPC分类号： G03F1/36

摘要： The manufacturability of a lithographic mask employed in fabricating instances of a semiconductor device is determined. Target edge pairs are selected from mask layout data of the lithographic mask to determine a manufacturing penalty in making the lithographic mask. The mask layout data includes polygons, where each polygon has edges, and where each target edge pair is defined by two of the edges of one or more of the polygons. The number of the target edge pairs is reduced to decrease computational volume in determining the manufacturing penalty in making the lithographic mask. The manufacturability of the lithographic mask, including the manufacturing penalty in making the lithographic mask, is determined based on the target edge pairs as reduced in number. The manufacturability of the lithographic mask is output. The manufacturability of the lithographic mask is dependent on the manufacturing penalty in making the lithographic mask.

摘要翻译： 确定用于制造半导体器件的实例的光刻掩模的可制造性。 从光刻掩模的掩模布局数据中选择目标边缘对，以确定在制作光刻掩模时的制造损失。 掩模布局数据包括多边形，其中每个多边形具有边缘，并且其中每个目标边对对由一个或多个多边形的两个边缘限定。 在确定制作光刻掩模时的制造损失时，减少目标边缘对的数量以减少计算量。 基于减少数量的目标边缘对来确定光刻掩模的可制造性，包括制造光刻掩模的制造损失。 输出光刻掩模的可制造性。 光刻掩模的可制造性取决于制造光刻掩模的制造损失。

公开(公告)号：US20110231803A1

公开(公告)日：2011-09-22

申请号：US12725287

申请日：2010-03-16

申请人： Tadanobu Inoue ,  David O. Melville ,  Hidemasa Muta ,  Alan E. Rosenbluth ,  Kehan Tian ,  Masaharu Sakamoto ,  Saeed Bagheri

发明人： Tadanobu Inoue ,  David O. Melville ,  Hidemasa Muta ,  Alan E. Rosenbluth ,  Kehan Tian ,  Masaharu Sakamoto ,  Saeed Bagheri

IPC分类号： G06F17/50

CPC分类号： G03F7/70433 ,  G03F1/36 ,  G03F1/70 ,  G03F7/705

摘要： Optical wave data for a semiconductor device design is divided into regions. First wavefront engineering is performed on the wave data of each region, accounting for just the wave data of each region and not accounting for the wave data of neighboring regions of each region. The optical wave data of each region is normalized based on results of the first wavefront engineering. Second wavefront engineering is performed on the wave data of each region, based at least on the wave data of each region as has been normalized. The second wavefront engineering takes into account the wave data of each region and a guard band around each region that includes the wave data of the neighboring regions of each region. The second wavefront engineering can be sequentially performed by organizing the regions into groups, and sequentially performing the second wavefront engineering on the regions of each group in parallel.

摘要翻译： 半导体器件设计的光波数据分为几个区域。 对每个区域的波形数据执行第一波前工程，仅考虑每个区域的波形数据，不考虑每个区域的相邻区域的波形数据。 基于第一波前工程的结果对每个区域的光波数据进行归一化。 至少基于已经归一化的每个区域的波形数据，对每个区域的波形数据执行第二波前工程。 第二波前工程考虑了每个区域的波形数据和围绕每个区域的保护带，其包括每个区域的相邻区域的波形数据。 可以通过将区域组合成组并且顺序地在并行地对每个组的区域执行第二波前工程来顺序执行第二波前工程。

公开(公告)号：US07844938B2

公开(公告)日：2010-11-30

申请号：US12109400

申请日：2008-04-25

申请人： Alan E. Rosenbluth ,  Ian P. Stobert

发明人： Alan E. Rosenbluth ,  Ian P. Stobert

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G03F1/36

摘要： A solution for performing a data correction on a hierarchical integrated circuit layout is provided. A method includes: receiving a CD compensation map for the long range critical dimension variation prior to the data correction; grouping compensation amounts of the CD compensation into multiple compensation ranges; generating multiple target layers corresponding to the multiple compensation ranges; super-imposing a region of the CD compensation map having a compensation amount falling into a compensation range over a respective target layer to generate a target shape; performing the data correction on the layout to generate a data corrected layout; performing the data correction on the target shape separately to generate a data corrected target shape; and combining the data corrected layout and the data corrected target shape based on the CD compensation map.

摘要翻译： 提供了一种用于在分层集成电路布局上执行数据校正的解决方案。 一种方法包括：在数据校正之前接收用于长距离临界尺寸变化的CD补偿图; 将CD补偿的补偿量分组为多个补偿范围; 产生对应于多个补偿范围的多个目标层; 超级CD补偿图的区域具有落在相应目标层上的补偿范围内的补偿量以产生目标形状; 在布局上执行数据校正以生成数据校正布局; 分别对目标形状进行数据校正，生成数据校正对象形状; 并且基于CD补偿图组合数据校正布局和数据校正目标形状。

公开(公告)号：US20100153903A1

公开(公告)日：2010-06-17

申请号：US12334488

申请日：2008-12-14

申请人： Tadanobu Inoue ,  David O. Melville ,  Hidemasa Muta ,  Kehan Tian ,  Masaharu Sakamoto ,  Alan E. Rosenbluth

发明人： Tadanobu Inoue ,  David O. Melville ,  Hidemasa Muta ,  Kehan Tian ,  Masaharu Sakamoto ,  Alan E. Rosenbluth

IPC分类号： G06F17/50

CPC分类号： G03F1/76 ,  G03F1/36

摘要： The manufacturability of a lithographic mask employed in fabricating instances of a semiconductor device is determined. Target edge pairs are selected from mask layout data of the lithographic mask, for determining a manufacturing penalty in making the lithographic mask. The mask layout data includes polygons, where each polygon has a number of edges. Each target edge pair is defined by two of the edges of one or more of the polygons. The manufacturability of the lithographic mask, including the manufacturing penalty in making the lithographic mask, is determined. Determining the manufacturing penalty is based on the target edge pairs as selected. Determining the manufacturability of the lithographic mask uses continuous derivatives characterizing the manufacturability of the lithographic mask on a continuous scale. The manufacturability of the lithographic mask is output. The manufacturability of the lithographic mask is dependent on the manufacturing penalty in making the lithographic mask.

摘要翻译： 确定用于制造半导体器件的实例的光刻掩模的可制造性。 从光刻掩模的掩模布局数据中选择目标边缘对，以确定在制作光刻掩模时的制造损失。 掩模布局数据包括多边形，其中每个多边形具有多个边。 每个目标边对由一个或多个多边形的两个边缘定义。 确定了光刻掩模的可制造性，包括制造光刻掩模的制造损失。 确定制造损失是基于所选择的目标边缘对。 确定平版印刷掩模的可制造性使用连续的衍生物来表征平版印刷掩模的可制造性在连续尺度上。 输出光刻掩模的可制造性。 光刻掩模的可制造性取决于制造光刻掩模的制造损失。

公开(公告)号：US20100153901A1

公开(公告)日：2010-06-17

申请号：US12334482

申请日：2008-12-14

申请人： Tadanobu Inoue ,  David O. Melville ,  Hidemasa Muta ,  Kehan Tian ,  Masaharu Sakamoto ,  Alan E. Rosenbluth

发明人： Tadanobu Inoue ,  David O. Melville ,  Hidemasa Muta ,  Kehan Tian ,  Masaharu Sakamoto ,  Alan E. Rosenbluth

IPC分类号： G06F17/50 ,  G03F1/00

CPC分类号： G03F1/36

摘要： The manufacturability of a lithographic mask employed in fabricating instances of a semiconductor device is determined. Target edge pairs are selected from mask layout data of the lithographic mask to determine a manufacturing penalty in making the lithographic mask. The mask layout data includes polygons, where each polygon has edges, and where each target edge pair is defined by two of the edges of one or more of the polygons. The number of the target edge pairs is reduced to decrease computational volume in determining the manufacturing penalty in making the lithographic mask. The manufacturability of the lithographic mask, including the manufacturing penalty in making the lithographic mask, is determined based on the target edge pairs as reduced in number. The manufacturability of the lithographic mask is output. The manufacturability of the lithographic mask is dependent on the manufacturing penalty in making the lithographic mask.

摘要翻译： 确定用于制造半导体器件的实例的光刻掩模的可制造性。 从光刻掩模的掩模布局数据中选择目标边缘对，以确定在制作光刻掩模时的制造损失。 掩模布局数据包括多边形，其中每个多边形具有边缘，并且其中每个目标边对对由一个或多个多边形的两个边缘限定。 在确定制作光刻掩模时的制造损失时，减少目标边缘对的数量以减小计算量。 基于减少数量的目标边缘对来确定光刻掩模的可制造性，包括制造光刻掩模的制造损失。 输出光刻掩模的可制造性。 光刻掩模的可制造性取决于制造光刻掩模的制造损失。

公开(公告)号：US07587702B2

公开(公告)日：2009-09-08

申请号：US11627418

申请日：2007-01-26

申请人： Alan E. Rosenbluth

发明人： Alan E. Rosenbluth

IPC分类号： G06F17/50 ,  G03C5/00

CPC分类号： G03F1/36

摘要： A set of candidate global optima is identified, one of which is a global solution for making a mask for printing a lithographic pattern. A solution space is formed from dominant joint eigenvectors that is constrained for bright and dark areas of the printed pattern. The solution space is mapped to identify regions each containing at most one local minimum intensity. For each selected region, stepped intensity contours are generated for intensity of the dark areas and stepped constraint surfaces are generated for a target exposure dose at an individual test point. An individual test point is stepped toward a lowest intensity contour along the stepped constraint surfaces of each selected region. Further lowering of the intensities of these points is also detailed, where possible in adjacent regions, to yield final test points. The set of candidate global optima is the final test points at their respective lowest intensity contour of the respective selected regions.

摘要翻译： 确定一组候选全局最优值，其中之一是制作用于印刷光刻图案的掩模的全球解决方案。 由占优的联合特征向量形成解决空间，该特征向量被限制在印刷图案的明暗区域。 映射空间被映射以识别每个最多包含一个局部最小强度的区域。 对于每个选择的区域，针对暗区的强度产生阶梯强度轮廓，并且在单个测试点处针对目标曝光剂量产生阶梯式约束表面。 单个测试点沿着每个选定区域的阶梯式约束表面朝向最低强度轮廓。 在相邻区域可能的情况下，这些点的强度进一步降低也是详细的，以产生最终的测试点。 候选全局最优的集合是各自选定区域各自最低强度轮廓的最终测试点。